Patents by Inventor Qiao Chen
Qiao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12255115Abstract: In examples, a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die. The semiconductor package has a surface and a cavity formed in the surface. The semiconductor device comprises an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound.Type: GrantFiled: March 26, 2024Date of Patent: March 18, 2025Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Christopher Daniel Manack, Patrick Francis Thompson, Qiao Chen
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Patent number: 12186806Abstract: The present disclosure provides a method for in-situ monitoring of a full cycle of spatter formation, ejection, and falling in laser additive manufacturing. In a spatter formation stage, a paraxial multiocular high-speed photographing apparatus is used to provide a high temporal-spatial resolution, accurately collect spatial positions of spatters at each sampling time, and reconstruct a motion trajectory of the spatters in three-dimensional (3D) space. In an ejection stage, a coaxial monocular high-speed photographing apparatus is used to provide a long-term high temporal-spatial resolution and accurately collect and count an ejection velocity and angle and a motion trajectory of the spatters, and a photodiode monitors a radiation intensity and changes of the spatters. In a falling stage, a multiocular photographing apparatus is used to provide a high spatial resolution covering an entire powder bed and collect a distribution state of falling spatters.Type: GrantFiled: March 15, 2024Date of Patent: January 7, 2025Assignee: CHINA UNIVERSITY OF GEOSCIENCES (WUHAN)Inventors: Jie Yin, Zuowei Yin, Kai Guan, Jinze Cheng, Xingyu Chen, Zheng Li, Qiao Chen, Tianye Huang, Andong Zhu, Shiyi Zhou
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Publication number: 20250006633Abstract: Embodiments of the present disclosure relate to an interconnect package, a method of forming the interconnect package, and a power module. The interconnect package includes a first insulating layer, a source connecting portion disposed on a surface of the first insulating layer and adapted to electrically connect a source pad to a substrate, a second insulating layer, and a gate connecting portion disposed between the first insulating layer and the second insulating layer and adapted to electrically connect a gate pad to the substrate.Type: ApplicationFiled: June 25, 2024Publication date: January 2, 2025Applicant: Shenzhen STS Microelectronics Co. LtdInventors: Qiao CHEN, Nan Nan ZHENG, Zhi Chang ZHANG
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Publication number: 20240363462Abstract: In some examples, a package comprises a die having a device side with circuitry formed therein; a passivation layer abutting the device side; and first and second vias coupling to the device side and extending through the passivation layer. The package includes first and second metal layers coupled to the first and second vias, respectively, the first and second metal layers abutting the passivation layer. The package includes an insulation layer abutting the first and second metal layers and separating the first and second metal layers, the insulation layer having an orifice in vertical alignment with the second metal layer. The package includes a third metal layer coupled to the second metal layer through the orifice, the third metal layer vertically aligned with the first and second metal layers. The package comprises a conductive member coupled to the third metal layer. The package includes a mold compound covering package components.Type: ApplicationFiled: April 28, 2023Publication date: October 31, 2024Inventors: Vivek Swaminathan SRIDHARAN, Hung-Yun LIN, Qiao CHEN
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Publication number: 20240234231Abstract: In examples, a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die. The semiconductor package has a surface and a cavity formed in the surface. The semiconductor device comprises an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound.Type: ApplicationFiled: March 26, 2024Publication date: July 11, 2024Inventors: Christopher Daniel MANACK, Patrick Francis THOMPSON, Qiao CHEN
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Patent number: 12024648Abstract: A graphene anti-corrosion coating is described that comprises an epoxy resin and graphene subjected to surface modification, where the addition amount of the graphene is 0.01-0.2 wt % of the total mass of coating solid. By performing surface treatment on the graphene, the dispersity of the graphene in the coating is improved, and the compactness of the coating is enhanced.Type: GrantFiled: November 28, 2019Date of Patent: July 2, 2024Assignee: Toray Industries, Inc.Inventors: Ke Wang, Yang Yang, Qiao Chen, Manabu Kawasaki
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Publication number: 20240203843Abstract: A semiconductor package is provided, including a package forming method and a power supply module. The semiconductor package may include a first chip comprising a first surface, and a second surface opposite the first surface. The semiconductor package may also include a chip interconnect component located on the second surface of the first chip. In addition, the semiconductor package may include a second chip located on the chip interconnect component, comprising a third surface in contact with the chip interconnect component, and a fourth surface opposite the third surface. The chip interconnect component comprises an electrically conductive frame, one side of the electrically conductive frame is electrically connected to the second surface of the first chip, and the other side of the electrically conductive frame is electrically connected to the third surface of the second chip.Type: ApplicationFiled: December 7, 2023Publication date: June 20, 2024Applicant: SHENZHEN STS MICROELECTRONICS CO., LTD.Inventors: Lin LIANG, Qiao CHEN, Junjie QIU, Yi Ming LIANG
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Patent number: 12009319Abstract: An integrated circuit (IC) die includes a substrate with circuitry configured for at least one function including metal interconnect levels thereon including a top metal interconnect level and a bottom metal interconnect level, with a passivation layer on the top metal interconnect level. A scribe street is around a periphery of the IC die, the scribe street including a scribe seal utilizing at least two of the plurality of metal interconnect levels, an inner metal meander stop ring including at least the top metal interconnect level located outside the scribe seal, wherein the scribe seal and the inner metal meander stop ring are separated by a first separation gap. An outer metal meander stop ring including at least the top metal interconnect level is located outside the inner metal stop ring, wherein the outer stop ring and the inner stop ring are separated by a second separation gap.Type: GrantFiled: January 8, 2020Date of Patent: June 11, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Christopher Daniel Manack, Qiao Chen, Michael Todd Wyant, Matthew John Sherbin, Patrick Francis Thompson
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Patent number: 11942386Abstract: In examples, a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die. The semiconductor package has a surface and a cavity formed in the surface. The semiconductor device comprises an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound.Type: GrantFiled: August 24, 2020Date of Patent: March 26, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Christopher Daniel Manack, Patrick Francis Thompson, Qiao Chen
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Patent number: 11881333Abstract: Disclosed are a ground terminal and an electronic device. The ground terminal includes a core body, a first bonding layer, a second bonding layer, a metal support plate, a third bonding layer, a fourth bonding layer, and a metal work piece. The metal support plate is attached to a lower part of the core body. The metal work piece includes a contact layer, a side layer, an upper welding layer, a wrapping layer, and a lower welding layer. The contact layer is attached to an upper part of the core body, the side layer is located on one side of the core body, the upper welding layer is connected to the metal support plate, the wrapping layer wraps an end portion of the metal support plate, the upper and lower welding layers are connected to a top end of the wrapping layer and the metal support plate, respectively.Type: GrantFiled: May 22, 2023Date of Patent: January 23, 2024Assignee: Shenzhen Johan Material Technology Co., Ltd.Inventors: Mujiu Chen, Jingyun Liu, Qiao Chen
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Patent number: 11855024Abstract: In some examples a wafer chip scale package (WCSP) includes a semiconductor die having a device side in which a circuit is formed, and a redistribution layer (RDL) coupled to the device side that is positioned within an insulating member. In addition, the WCSP includes a scribe seal circumscribing the circuit along the device side, wherein the RDL abuts the scribe seal. Further, the WCSP includes a conductive member coupled to the RDL. The conductive member is configured to receive a solder member, and the insulating member does not extend along the device side of the semiconductor die between the conductive member and a portion of an outer perimeter of the WCSP closest to the conductive member.Type: GrantFiled: August 31, 2021Date of Patent: December 26, 2023Assignee: Texas Instruments IncorporatedInventors: Qiao Chen, Vivek Swaminathan Sridharan, Christopher Daniel Manack, Patrick Francis Thompson, Jonathan Andrew Montoya, Salvatore Frank Pavone
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Patent number: 11727325Abstract: Systems, methods, and techniques to efficiently analyze and navigate through decision logic using an execution graph are provided. The method includes executing decision logic in response to receiving a data file. The method further includes generating, in response to the executing, an execution graph. The execution graph includes a plurality of nodes corresponding to a plurality of decision entities of the decision logic. The method further includes displaying the execution graph on a user interface. The method further includes displaying, in response to receiving a selection of a node of the plurality of nodes, information associated with the selected node.Type: GrantFiled: August 1, 2018Date of Patent: August 15, 2023Assignee: Fair Isaac CorporationInventors: Jean-Luc M. Marcé, Balachandar Rangarajulu Sriramulu, Imran Ali, Qiao Chen
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Patent number: 11646509Abstract: A grounding elastic contact and an electronic device including the same. The grounding elastic contact includes an elastic core, and a double-sided polyethylene terephthalate (PET) tape, a polyimide (PI) film, and a conductive layer, where the PI film is laminated and bonded on an outer side of the double-sided PET tape; a middle region of the double-sided PET tape is attached to an upper surface of the elastic core; after passing through left and right sides of the elastic core respectively, two ends of the double-sided PET tape are laminated on a lower surface of the elastic core; the conductive layer includes one end bonded on the upper surface of the elastic core, and the other end passing through the left side of the elastic core; the double-sided PET tape includes a PET backing and an adhesive coated on two sides of the PET backing.Type: GrantFiled: July 6, 2022Date of Patent: May 9, 2023Assignee: Shenzhen Johan Material Technology Co., Ltd.Inventors: Mujiu Chen, Fang Chen, Qiao Chen, Jingyun Liu
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Publication number: 20230093996Abstract: A grounding elastic contact and an electronic device including the same. The grounding elastic contact includes an elastic core, and a double-sided polyethylene terephthalate (PET) tape, a polyimide (PI) film, and a conductive layer, where the PI film is laminated and bonded on an outer side of the double-sided PET tape; a middle region of the double-sided PET tape is attached to an upper surface of the elastic core; after passing through left and right sides of the elastic core respectively, two ends of the double-sided PET tape are laminated on a lower surface of the elastic core; the conductive layer includes one end bonded on the upper surface of the elastic core, and the other end passing through the left side of the elastic core; the double-sided PET tape includes a PET backing and an adhesive coated on two sides of the PET backing.Type: ApplicationFiled: July 6, 2022Publication date: March 30, 2023Inventors: Mujiu Chen, Fang Chen, Qiao Chen, Jingyun Liu
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Patent number: 11615606Abstract: A tree crown extraction method based on UAV multi-source remote sensing includes: obtaining a visible light image and LIDAR point clouds, taking a digital orthophoto map (DOM) and the LIDAR point clouds as data sources, using a method of watershed segmentation and object-oriented multi-scale segmentation to extract single tree crown information under different canopy densities. The object-oriented multi-scale segmentation method is used to extract crown and non-crown areas, and a tree crown distribution range is extracted with the crown area as a mask; a preliminary segmentation result of single tree crown is obtained by the watershed segmentation method based on a canopy height model; a brightness value of DOM is taken as a feature, the crown area of the DOM is performed secondary segmentation based on a crown boundary to obtain an optimized single tree crown boundary information, which greatly increases the accuracy of remote sensing tree crown extraction.Type: GrantFiled: August 8, 2022Date of Patent: March 28, 2023Assignee: INSTITUTE OF FOREST RESOURCE INFORMATION TECHNIQUES CAFInventors: Qiao Chen, Yongfu Chen, Juan Wang, Zhiyang Xu
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Publication number: 20230065075Abstract: In some examples a wafer chip scale package (WCSP) includes a semiconductor die having a device side in which a circuit is formed, and a redistribution layer (RDL) coupled to the device side that is positioned within an insulating member. In addition, the WCSP includes a scribe seal circumscribing the circuit along the device side, wherein the RDL abuts the scribe seal. Further, the WCSP includes a conductive member coupled to the RDL. The conductive member is configured to receive a solder member, and the insulating member does not extend along the device side of the semiconductor die between the conductive member and a portion of an outer perimeter of the WCSP closest to the conductive member.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Qiao CHEN, Vivek Swaminathan SRIDHARAN, Christopher Daniel MANACK, Patrick Francis THOMPSON, Jonathan Andrew MONTOYA, Salvatore Frank PAVONE
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Patent number: D1038318Type: GrantFiled: April 26, 2024Date of Patent: August 6, 2024Inventor: Qiao Chen
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Patent number: D1038319Type: GrantFiled: April 26, 2024Date of Patent: August 6, 2024Inventor: Qiao Chen
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Patent number: D1046066Type: GrantFiled: May 29, 2024Date of Patent: October 8, 2024Inventor: Qiao Chen
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Patent number: D1048295Type: GrantFiled: June 21, 2024Date of Patent: October 22, 2024Inventor: Qiao Chen