Patents by Inventor Qiao Yuan

Qiao Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250005541
    Abstract: The present disclosure provides a digital currency transaction method and system, and related transaction terminals, and relates to the field of computer technology. A specific implementation of the method includes: exchanging, by a first transaction terminal, user certificates with a second transaction terminal to verify user identities of the two parties after establishing a communication connection with the second transaction terminal, negotiating with the second transaction terminal to generate a transaction factor after confirming that the user identity verification of the two parties succeeds, and uploading first digital currency transaction information including the transaction factor to a first operating institution back-end system, and sending, by the first operating institution back-end system, the first digital currency transaction information to a second operating institution back-end system to complete the digital currency transaction.
    Type: Application
    Filed: October 26, 2022
    Publication date: January 2, 2025
    Inventors: Changchun MU, Gang DI, Peidong CUI, Xinyu ZHAO, Jianchang GUO, Qiao YUAN
  • Patent number: 8765495
    Abstract: A method of forming a pattern of doped region includes the following steps. At first, a device layout pattern including a gate layout pattern and a doped region layout pattern is provided to a computer system. Subsequently, the device layout pattern is split into a plurality of sub regions, and the sub regions have different pattern densities of the gate layout pattern. Then, at least an optical proximity correction (OPC) calculation is respectively performed on the doped region layout pattern in each of the sub regions to respectively form a corrected sub doped region layout pattern in each of the sub regions. Afterwards, the corrected sub doped region layout patterns are combined to form a corrected doped region layout pattern, and the corrected doped region layout pattern is outputted onto a mask through the computer system.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: July 1, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Hsiu Lee, Guo-Xin Hu, Qiao-Yuan Liu, Yen-Sheng Wang
  • Publication number: 20120132702
    Abstract: A test assist device includes: a network function module having a network port that is connectible to a network device; a control module connected to the network function module and having a processing unit and a transmission port electrically connectible to an input unit for receiving from the input unit at least one of basic test data and test result messages of an object, the processing unit transmitting the received at least one of the basic test data and the test result messages via the network function module to the network device; and an output module connected to the control module and having a basic status prompt unit and a test result prompt unit, the basic status prompt unit having a plurality of LEDs for displaying corresponding information corresponding to the basic test data, the test result prompt unit displaying corresponding information corresponding to the test result messages.
    Type: Application
    Filed: December 7, 2010
    Publication date: May 31, 2012
    Applicant: Askey Computer Corporation
    Inventors: Qiao Yuan, Coast Zhou, Ching-Feng Hsieh