Abstract: A computer-implemented method includes modeling, using the computer, a photoresist profile in accordance with a magnitude of a gradient of an inhibitor concentration disposed in the photoresist. The photoresist is used during a process to form an integrated circuit. In one embodiment, the computer-implemented method further includes applying the modeled photoresist profile to reduce a distortion in a printed photoresist pattern caused by a response of the photoresist to an electromagnetic wave and/or particle beam during the process.

Abstract: A computer-implemented method includes characterizing, using the computer, a photoresist profile in accordance with a magnitude of a gradient of an inhibitor concentration disposed in the photoresist.

Abstract: One embodiment of the present invention provides a system that accurately models polarization states of an illumination source in an optical lithography system for manufacturing integrated circuits. During operation, the system starts by receiving a two-dimensional (2D) grid map for an illumination source pupil in the optical lithography system. The system then constructs a source-polarization model for the illumination source by defining a polarization state at each grid point in the grid map. Next, the system enhances a lithography model for the optical lithography system by incorporating the source-polarization model into the lithography/OPC model.

Abstract: One embodiment of the present invention provides a system that determines image intensity at a location in a photoresist (PR) layer on a wafer. During operation, the system receives a set of masks which were used to generate one or more patterned layers of a multilayer structure on the wafer, wherein a patterned layer includes a set of reflectors on a top surface of the patterned layer, which correspond to patterns in a patterned-layer mask in the set of masks, wherein a reflector reflects light from a light source during a photolithography process. The system then generates a first virtual mask based on the first mask and the patterned-layer mask, wherein the first virtual mask uses a clear area to model a reflector in the set of reflectors. Next, the system determines the image intensity value at the location on the PR layer based at least on the first mask and the first virtual mask.

Abstract: One embodiment of the present invention relates to a process that models critical-dimension (CD) scanning-electron-microscopy (CD-SEM) extraction during photolithography process model calibration. During operation, the process receives measured CD values which were obtained using a CD-SEM extraction process, wherein the CD-SEM extraction process determines a measured CD value for a feature by measuring multiple CD values of the feature along multiple electron beam scans. The process then determines simulated CD values, wherein a simulated CD value is determined based at least on a set of CD extraction cut-lines evenly placed around the target feature. During subsequent photolithography process model calibration, the process fits a parameter that models an aspect of the photolithography process based at least on both the measured CD values and the simulated CD values.

Abstract: A method is described herein for predicting lateral position information about a feature represented in an integrated circuit layout for use with an integrated circuit fabrication process, where the process projects an image onto a resist. The method includes providing a lateral distribution of intensity values of the image at different depths with the resist. Next, the lateral position of an edge point of the feature is predicted in dependence upon a particular resist development time, and further in dependence upon the image intensity values at more than one depth within the resist.

Abstract: One embodiment of the present invention provides a system that determines image intensity at a location in a photoresist (PR) layer on a wafer. During operation, the system receives a set of masks which were used to generate one or more patterned layers of a multilayer structure on the wafer, wherein a patterned layer includes a set of reflectors on a top surface of the patterned layer, which correspond to patterns in a patterned-layer mask in the set of masks, wherein a reflector reflects light from a light source during a photolithography process. The system then generates a first virtual mask based on the first mask and the patterned-layer mask, wherein the first virtual mask uses a clear area to model a reflector in the set of reflectors. Next, the system determines the image intensity value at the location on the PR layer based at least on the first mask and the first virtual mask.

Abstract: One embodiment of the present invention relates to a process that models critical-dimension (CD) scanning-electron-microscopy (CD-SEM) extraction during photolithography process model calibration. During operation, the process receives measured CD values which were obtained using a CD-SEM extraction process, wherein the CD-SEM extraction process determines a measured CD value for a feature by measuring multiple CD values of the feature along multiple electron beam scans. The process then determines simulated CD values, wherein a simulated CD value is determined based at least on a set of CD extraction cut-lines evenly placed around the target feature. During subsequent photolithography process model calibration, the process fits a parameter that models an aspect of the photolithography process based at least on both the measured CD values and the simulated CD values.

Abstract: One embodiment of the present invention provides a system that accurately predicts an apodization effect in an optical lithography system for manufacturing an integrated circuit. During operation, the system starts by collecting an apodization-effect-induced spatial transmission profile from the optical lithography system. The system then constructs an apodization model based on the spatial transmission profile. Next, the system enhances a lithography model for the optical lithography system by incorporating the apodization model into the lithography model, wherein the enhanced lithography model accurately predicts the effects of apodization on the optical lithography system.

Abstract: A method is described herein for predicting lateral position information about a feature represented in an integrated circuit layout for use with an integrated circuit fabrication process, where the process projects an image onto a resist. The method includes providing a lateral distribution of intensity values of the image at different depths with the resist. Next, the lateral position of an edge point of the feature is predicted in dependence upon a particular resist development time, and further in dependence upon the image intensity values at more than one depth within the resist.

Abstract: One embodiment of the present invention provides a system that constructs a source polarization model to simulate a piecewise-constant-linear polarization-configuration of an illumination source in an optical lithography system. During operation, the system starts by partitioning an illumination pupil plane of the illumination source into a set of sectors to match a physical implementation of the illumination source. Next, the system constructs the source polarization model for the illumination source by individually specifying a constant-linear polarization-state within each sector to match the polarization-configuration of the illumination source.

Abstract: One embodiment of the present invention provides a system that accurately models polarization states of an illumination source in an optical lithography system for manufacturing integrated circuits. During operation, the system starts by receiving a two-dimensional (2D) grid map for an illumination source pupil in the optical lithography system. The system then constructs a source-polarization model for the illumination source by defining a polarization state at each grid point in the grid map. Next, the system enhances a lithography model for the optical lithography system by incorporating the source-polarization model into the lithography/OPC model.

Abstract: One embodiment of the present invention provides a system that accurately models polarization effects in an optical lithography system for manufacturing integrated circuits. During operation, the system starts by receiving a polarization-description grid map for a lens pupil in the optical lithography system. The system then constructs a pupil-polarization model by defining a vectorial matrix at each grid point in the grid map, wherein the vectorial matrix specifies a pupil-induced polarization effect on an incoming optical field at the grid point. Next, the system enhances a lithography model for the optical lithography system by incorporating the pupil-polarization model into the lithography/OPC model. The system then uses the enhanced lithography model to perform convolutions with circuit patterns on a mask in order to simulate optical lithography pattern printing.

Abstract: One embodiment of the present invention provides a system that accurately predicts an apodization effect in an optical lithography system for manufacturing an integrated circuit. During operation, the system starts by collecting an apodization-effect-induced spatial transmission profile from the optical lithography system. The system then constructs an apodization model based on the spatial transmission profile. Next, the system enhances a lithography model for the optical lithography system by incorporating the apodization model into the lithography model, wherein the enhanced lithography model accurately predicts the effects of apodization on the optical lithography system.

Abstract: A system for optimizing critical dimension uniformity in semiconductor manufacturing processes is provided. The system comprises a bake plate simulator to model a physical bake plate. A finite element analysis engine uses information from the bake plate simulator to calculate missing information. A lithography simulator predicts outcomes of a lithography process using information from the bake plate simulator and the finite element analysis engine. The system can be used in a predictive capacity or as part of a process control system.