Abstract: A multi-chip interconnection system includes a plurality of chips. A chip of the plurality of chips includes an extend serial peripheral interface (XSPI) master terminal, a data transmission terminal, an XSPI slave terminal, and a data reception terminal. The XSPI master terminal includes an advanced extensible interface (AXI) slave interface. The data transmission terminal accesses the AXI slave interface via an AXI bus. The XSPI slave terminal includes an AXI master interface. The data reception terminal accesses the AXI master interface via the AXI bus. An XSPI master terminal of a chip is connected to an XSPI slave terminal of another chip via an XSPI bus. The XSPI master terminal of the chip performs encoding on AXI information of the data transmission terminal of the chip received via the AXI bus and transmits encoded AXI information to the XSPI slave terminal of the another chip via the XSPI bus.

Abstract: A display controller having an automatic data underrun recovery function, comprising: a direct memory access (DMA) controller coupled to an image data processor; the image data processor coupled to an image layer synthesizer; the image layer synthesizer coupled to a first-in first-out (FIFO) memory; a display timing generation circuit (DTC) coupled to the FIFO memory, the display timing generation circuit (DTC) being coupled to an external display device; and an underrun state machine separately coupled to the display timing generation circuit (DTC), an underload data counter, the DMA controller, the image data processor, the image layer synthesizer, and the FIFO memory. The provided display controller has an automatic data underrun recovery function.

Abstract: A data access method includes obtaining a data access request for M storage devices, M being an integer greater than or equal to 2, determining a target access mode for the M storage devices based on the data access request, and performing data access on the storage devices based on access control signals matching the target access mode for the storage devices. The target access mode includes a first access mode and a second access mode. Access security and/or access speed generated when the data access is performed on the storage devices in the first access mode is different from access security and/or access speed generated in the second access mode.

Abstract: A display controller having an automatic data underrun recovery function, comprising: a direct memory access (DMA) controller coupled to an image data processor; the image data processor coupled to an image layer synthesizer; the image layer synthesizer coupled to a first-in first-out (FIFO) memory; a display timing generation circuit (DTC) coupled to the FIFO memory, the display timing generation circuit (DTC) being coupled to an external display device; and an underrun state machine separately coupled to the display timing generation circuit (DTC), an underload data counter, the DMA controller, the image data processor, the image layer synthesizer, and the FIFO memory. The provided display controller has an automatic data underrun recovery function.

Abstract: A multi-chip interconnection system includes a plurality of chips. A chip of the plurality of chips includes an extend serial peripheral interface (XSPI) master terminal, a data transmission terminal, an XSPI slave terminal, and a data reception terminal. The XSPI master terminal includes an advanced extensible interface (AXI) slave interface. The data transmission terminal accesses the AXI slave interface via an AXI bus. The XSPI slave terminal includes an AXI master interface. The data reception terminal accesses the AXI master interface via the AXI bus. An XSPI master terminal of a chip is connected to an XSPI slave terminal of another chip via an XSPI bus. The XSPI master terminal of the chip performs encoding on AXI information of the data transmission terminal of the chip received via the AXI bus and transmits encoded AXI information to the XSPI slave terminal of the another chip via the XSPI bus.

Abstract: A camera interface circuit for a barcode scanner includes a binary conversion block and a selection module. The binary conversion block receives image signals from a camera, and converts gray levels of each pixel in each image frame into binary codes. The selection module alternately provides binary codes of one image frame and image signals of a consecutive image frame as outputs.

Abstract: A camera interface circuit for a barcode scanner includes a binary conversion block and a selection module. The binary conversion block receives image signals from a camera, and converts gray levels of each pixel in each image frame into binary codes. The selection module alternately provides binary codes of one image frame and image signals of a consecutive image frame as outputs.