Abstract: A method for transmitting an audio-video data can include: receiving a video signal from a video source and an audio signal from an audio source; receiving an audio data of the audio signal, and detecting an audio frame clock signal of the audio signal; converting the audio data to an audio data sequence with a first encoding rule; generating a start data code, an end data code, and an audio frame clock code according to the audio data sequence and the audio frame clock signal with a second encoding rule, where the first encoding rule is different than the second encoding rule; generating a low speed data frame according to the audio frame clock signal and the audio data sequence; inserting the start data code at the beginning of each audio data sequence, and inserting the end data code at the ending of each audio data sequence.

Abstract: The present disclosure relates to a class-D audio amplifier. When the class-D audio amplifier is powered on, an auxiliary power amplifier and an auxiliary feedback circuit constitute an auxiliary close loop so that a control loop is established in advance. The auxiliary close loop is disconnected after various circuit modules reach their steady operation points, and the class-D audio amplifier operates at a normal state. A soft start circuit is provided for suppressing noise which occurs when the class-D audio amplifier is powered on. Thus, the class-D audio amplifier suppresses POP noise at an output terminal when the class-D audio amplifier is powered on.

Abstract: A method for transmitting an audio-video data can include: receiving a video signal from a video source and an audio signal from an audio source; receiving an audio data of the audio signal, and detecting an audio frame clock signal of the audio signal; converting the audio data to an audio data sequence with a first encoding rule; generating a start data code, an end data code, and an audio frame clock code according to the audio data sequence and the audio frame clock signal with a second encoding rule, where the first encoding rule is different than the second encoding rule; generating a low speed data frame according to the audio frame clock signal and the audio data sequence; inserting the start data code at the beginning of each audio data sequence, and inserting the end data code at the ending of each audio data sequence.

Abstract: An audio processing integrated circuit chip, such as codec chip, includes at least one port output circuit configured to generate an audio signal to drive an external audio device and a PC beep circuit configured to receive a PC beep signal and to apply the received PC beep signal to an input of the at least one port output circuit. The chip further includes a control circuit configured to detect activity of the PC beep signal and to enable and/or disable the at least one port output circuit responsive to the detected activity.

Abstract: The present disclosure relates to a class-D audio amplifier. When the system is powered on, an auxiliary power amplifier and an auxiliary feedback circuit constitute an auxiliary close loop so that a control loop is established in advance. The auxiliary close loop is disconnected after various circuit modules reach their steady operation points, and the system operates at a normal state. A soft start circuit is provided for suppressing noise which occurs when the system is powered on. Thus, the class-D audio amplifier suppresses POP noise at an output terminal when the system is powered on.

Abstract: A novel solution that combines the technologies of fractional divider and phase selection is provided to implement over-clocking for CPU PLL in PC clock generator with a set resolution that is independent of the clock frequency.

Abstract: A method and apparatus for generating a spread spectrum reference clock is presented. A method and apparatus is presented for receiving a spread spectrum parameter from a phase lock loop, wherein the spread spectrum parameter includes a multiple-level parameter comprising a plurality of phase signals; quantizing a spread spectrum profile associated with the spread spectrum parameter; mapping the quantized profile; generating control signals based on the mapping, wherein the control signals include an integer control signal and a phase control signal; dividing a phase signal of the plurality of phase signals with the integer control signal; synchronizing the divided phase signal using the phase control signal; and providing a reference clock for a spread spectrum clock generator based on the synchronizing.

Abstract: A novel solution that combines the technologies of fractional divider and phase selection is provided to implement over-clocking for CPU PLL in PC clock generator with a set resolution that is independent of the clock frequency.

Abstract: A method and apparatus for generating a spread spectrum reference clock is presented. A method and apparatus is presented for receiving a spread spectrum parameter from a phase lock loop, wherein the spread spectrum parameter includes a multiple-level parameter comprising a plurality of phase signals; quantizing a spread spectrum profile associated with the spread spectrum parameter; mapping the quantized profile; generating control signals based on the mapping, wherein the control signals include an integer control signal and a phase control signal; dividing a phase signal of the plurality of phase signals with the integer control signal; synchronizing the divided phase signal using the phase control signal; and providing a reference clock for a spread spectrum clock generator based on the synchronizing.