Abstract: An Android-based system for touch input handling is provided. The system includes an interactive hardware and an application processor. The interactive hardware includes a display panel and a touch panel that runs a touch firmware. The application processor is coupled to the interactive hardware, and runs an application program and a touch driver. The application processor further converts a hardware synchronization signal of the display panel into a software synchronization signal, and generates an application synchronization signal based on the software synchronization signal. Additionally, the application processor further generates an input synchronization signal that is synchronized with the application synchronization signal. The expiration of the input synchronization signal triggers the touch firmware to collect the touch event and propagate the touch event up to the application program through the touch driver.

Abstract: A reduced instruction set computer (RISC)-V vector extension (RVV) core communicated with one or more accelerators. The RVV core includes: a command queue configured to output commands; and an interface unit communicatively coupled to the command queue and having circuitry configured to generate an accelerator command to an accelerator of the one or more accelerators based on the output commands.

Abstract: A computer-implemented method for allocating memory bandwidth of multiple CPU cores in a server includes: receiving an access request to a last level cache (LLC) shared by the multiple CPU cores in the server, the access request being sent from a core with a private cache holding copies of frequently accessed data from a memory; determining whether the access request is an LLC hit or an LLC miss; and controlling a memory bandwidth controller based on the determination. The memory bandwidth controller performs a memory bandwidth throttling to control a request rate between the private cache and the last level cache. The LLC hit of the access request causes the memory bandwidth throttling initiated by the memory bandwidth controller to be disabled and the LLC miss of the access request causes the memory bandwidth throttling initiated by the memory bandwidth controller to be enabled.

Abstract: The present application discloses a computing system and an associated method. The computing system includes a memory, a master computing device and a slave computing device. The master computing device includes a memory controller and an input-output memory management unit (IOMMU). When the slave computing device accesses a first virtual address, and a first translation lookaside buffer (TLB) of the slave computing device does not store the first virtual address, the first TLB sends a translation request to the IOMMU. The IOMMU traverses page tables of the memory controller to obtain a first physical address corresponding to the first virtual address, selects and clears a first virtual address entry from a second TLB of the computing system according to a recent use time and a dependent workload of each virtual address entry to store the first virtual address and the first physical address.

Abstract: Embodiments of the present disclosure includes a processor. The processor may include a systolic array of processing elements; a first group of buffers coupled to the systolic array, wherein the first group comprises one or more first buffers; a second group of buffers coupled to the systolic array, wherein the second group comprises one or more second buffers; an accumulator coupled to the systolic array; and a third group of buffers coupled to the accumulator, wherein the third group comprises one or more third buffers.