Abstract: Embodiments of the claimed subject matter provide a method and apparatus for performing pipelined operations on input data with feedback. One embodiment of the apparatus includes a first logic circuit for determining a value of a first function based on input data for a first clock cycle. The first logic circuit includes pipeline stages that perform subsets of calculations of the value of the first function in one clock cycle. The apparatus also includes a second logic circuit for determining a value of a second function for the first clock cycle based on a value of a third function for a second clock cycle prior to the first clock cycle. The apparatus further includes a third logic circuit for determining a value of the third function for the first clock cycle by combining the values of the first and second functions for the first clock cycle.

Abstract: Embodiments of the claimed subject matter provide a method and apparatus for performing pipelined operations on input data with feedback. One embodiment of the apparatus includes a first logic circuit for determining a value of a first function based on input data for a first clock cycle. The first logic circuit includes pipeline stages that perform subsets of calculations of the value of the first function in one clock cycle. The apparatus also includes a second logic circuit for determining a value of a second function for the first clock cycle based on a value of a third function for a second clock cycle prior to the first clock cycle. The apparatus further includes a third logic circuit for determining a value of the third function for the first clock cycle by combining the values of the first and second functions for the first clock cycle.

Abstract: The present invention discloses a method of processing a generic framing procedure (GFP) frame, the method includes the steps of: processing the GFP frame by the compensating process of payload area descrambler error multiplication factor; and processing the GFP frame by the process of tHEC or/and eHEC single-bit error correction. According to the present invention, not only a tHEC or/and eHEC single-bit error can be corrected, but also the tHEC or/and eHEC additional single-bit error can also be corrected so that the equipment's dependability and capability of anti-interference are improved significantly.

Abstract: The present invention discloses a method of processing a generic framing procedure (GFP) frame, the method includes the steps of: processing the GFP frame by the compensating process of payload area descrambler error multiplication factor; and processing the GFP frame by the process of tHEC or/and eHEC single-bit error correction. According to the present invention, not only a tHEC or/and eHEC single-bit error can be corrected, but also the tHEC or/and eHEC additional single-bit error can also be corrected so that the equipment's dependability and capability of anti-interference are improved significantly.