Abstract: Embodiments described herein may be useful in the detection of analytes. The systems and methods may allow for a relatively simple and rapid way for detecting analytes such as chemical and/or biological analytes and may be useful in numerous applications including sensing, food manufacturing, medical diagnostics, performance materials, dynamic lenses, water monitoring, environmental monitoring, detection of proteins, detection of DNA, among other applications. For example, the systems and methods described herein may be used for determining the presence of a contaminant such as bacteria (e.g., detecting pathogenic bacteria in food and water samples which helps to prevent widespread infection, illness, and even death). Advantageously, the systems and methods described herein may not have the drawbacks in current detection technologies including, for example, relatively high costs, long enrichment steps and analysis times, and/or the need for extensive user training.

Abstract: Embodiments described herein may be useful in the detection of analytes. The systems and methods may allow for a relatively simple and rapid way for detecting analytes such as chemical and/or biological analytes and may be useful in numerous applications including sensing, food manufacturing, medical diagnostics, performance materials, dynamic lenses, water monitoring, environmental monitoring, detection of proteins, detection of DNA, among other applications. For example, the systems and methods described herein may be used for determining the presence of a contaminant such as bacteria (e.g., detecting pathogenic bacteria in food and water samples which helps to prevent widespread infection, illness, and even death). Advantageously, the systems and methods described herein may not have the drawbacks in current detection technologies including, for example, relatively high costs, long enrichment steps and analysis times, and/or the need for extensive user training.

Abstract: Embodiment techniques map parity bits to sub-channels based on their row weights. In one example, an embodiment technique includes allocating, from a set of sub-channels, one or more sub-channels for one or more parity bits based on row weights for sub-channels in a subset of sub-channels within the set of sub-channels, mapping information bits to remaining sub-channels in the set of sub-channels based on a reliability of the remaining sub-channels without mapping any of the information bits to the one or more sub-channels allocated for the one or more parity bits, polar encoding the information bits and the one or more parity bits based on at least the mapping of the information bits to the remaining sub-channels to obtain encoded bits, and transmitting the encoded bits to another device.

Abstract: Embodiment techniques map parity bits to sub-channels based on their row weights. In one example, an embodiment technique includes polar encoding, with an encoder of the device, information bits and at least one parity bit using the polar code to obtain encoded data, and transmitting the encoded data to another device. The polar code comprises a plurality of sub-channels. The at least one parity bit being placed in at least one of the plurality of sub-channels. The at least one sub-channel is selected from the plurality of sub-channels based on a weight parameter.

Abstract: Embodiments are provided for an asynchronous processor with heterogeneous processors. In an embodiment, the apparatus for an asynchronous processor comprises a memory configured to cache instructions, and a first unit (XU) configured to processing a first instruction of the instructions. The apparatus also comprises a second XU having less restricted access than the first XU to a resource of the asynchronous processor and configured to process a second instruction of the instructions. The second instruction requires access to the resource. The apparatus further comprises a feedback engine configured to decode the first instruction and the second instruction, and issue the first instruction to the first XU, and a scheduler configured to send the second instruction to the second XU.

Abstract: Embodiments described herein may be useful in the detection of analytes. The systems and methods may allow for a relatively simple and rapid way for detecting analytes such as chemical and/or biological analytes and may be useful in numerous applications including sensing, food manufacturing, medical diagnostics, performance materials, dynamic lenses, water monitoring, environmental monitoring, detection of proteins, detection of DNA, among other applications. For example, the systems and methods described herein may be used for determining the presence of a contaminant such as bacteria (e.g., detecting pathogenic bacteria in food and water samples which helps to prevent widespread infection, illness, and even death). Advantageously, the systems and methods described herein may not have the drawbacks in current detection technologies including, for example, relatively high costs, long enrichment steps and analysis times, and/or the need for extensive user training.

Abstract: An asynchronous processing system comprising an asynchronous scalar processor and an asynchronous vector processor coupled to the scalar processor. The asynchronous scalar processor is configured to perform processing functions on input data and to output instructions. The asynchronous vector processor is configured to perform processing functions in response to a very long instruction word (VLIW) received from the scalar processor. The VLIW comprises a first portion and a second portion, at least the first portion comprising a vector instruction.

Abstract: Embodiments are provided for an asynchronous processor with token-based very long instruction word architecture. The asynchronous processor comprises a memory configured to cache a plurality of instructions, a feedback engine configured to receive the instructions in bundles of instructions at a time (referred to as very long instruction word) and to decode the instructions, and a crossbar bus configured to transfer calculation information and results of the asynchronous processor. The apparatus further comprises a plurality of sets of execution units (XUs) between the feedback engine and the crossbar bus. Each set of the sets of XUs comprises a plurality of XUs arranged in series and configured to process a bundle of instructions received at the each set from the feedback engine.

Abstract: Embodiments described herein may be useful in the detection of analytes. The systems and methods may allow for a relatively simple and rapid way for detecting analytes such as chemical and/or biological analytes and may be useful in numerous applications including sensing, food manufacturing, medical diagnostics, performance materials, dynamic lenses, water monitoring, environmental monitoring, detection of proteins, detection of DNA, among other applications. For example, the systems and methods described herein may be used for determining the presence of a contaminant such as bacteria (e.g., detecting pathogenic bacteria in food and water samples which helps to prevent widespread infection, illness, and even death). Advantageously, the systems and methods described herein may not have the drawbacks in current detection technologies including, for example, relatively high costs, long enrichment steps and analysis times, and/or the need for extensive user training.

Abstract: Embodiment techniques map parity bits to sub-channels based on their row weights. The row weight for a sub-channel may be viewed as the number of “ones” in the corresponding row of the Kronecker matrix or as a power of 2 with the exponent (i.e. the hamming weight) being the number of “ones” in the binary representation of the sub-channel index (further described below). In one embodiment, candidate sub-channels that have certain row weight values are reserved for parity bit(s). Thereafter, K information bits may be mapped to the K most reliable remaining sub-channels, and a number of frozen bits (e.g. N?K) may be mapped to the least reliable remaining sub-channels. Parity bits may then mapped to the candidate sub-channels, and parity bit values are determined based on a function of the information bits.

Abstract: Embodiment techniques map parity bits to sub-channels based on their row weights. The row weight for a sub-channel may be viewed as the number of “ones” in the corresponding row of the Kronecker matrix or as a power of 2 with the exponent (i.e. the hamming weight) being the number of “ones” in the binary representation of the sub-channel index (further described below). In one embodiment, candidate sub-channels that have certain row weight values are reserved for parity bit(s). Thereafter, K information bits may be mapped to the K most reliable remaining sub-channels, and a number of frozen bits (e.g. N?K) may be mapped to the least reliable remaining sub-channels. Parity bits may then mapped to the candidate sub-channels, and parity bit values are determined based on a function of the information bits.

Abstract: A clock-less asynchronous processor comprising a plurality of parallel asynchronous processing logic circuits, each processing logic circuit configured to generate an instruction execution result. The processor comprises an asynchronous instruction dispatch unit coupled to each processing logic circuit, the instruction dispatch unit configured to receive multiple instructions from memory and dispatch individual instructions to each of the processing logic circuits. The processor comprises a crossbar coupled to an output of each processing logic circuit and to the dispatch unit, the crossbar configured to store the instruction execution results.

Abstract: A clock-less asynchronous processing circuit or system having a plurality of pipelined processing stages utilizes self-clocked generators to tune the delay needed in each of the processing stages to complete the processing cycle. Because different processing stages may require different amounts of time to complete processing or may require different delays depending on the processing required in a particular stage, the self-clocked generators may be tuned to each stage's necessary delay(s) or may be programmably configured.

Abstract: Embodiments are provided for an asynchronous processor using master and assisted tokens. In an embodiment, an apparatus for an asynchronous processor comprises a memory to cache a plurality of instructions, a feedback engine to decode the instructions from the memory, and a plurality of XUs coupled to the feedback engine and arranged in a token ring architecture. Each one of the XUs is configured to receive an instruction of the instructions form the feedback engine, and receive a master token associated with a resource and further receive an assisted token for the master token. Upon determining that the assisted token and the master token are received in an abnormal order, the XU is configured to detect an operation status for the instruction in association with the assisted token, and upon determining a needed action in accordance with the operation status and the assisted token, perform the needed action.

Abstract: A clock-less asynchronous processing circuit or system utilizes a self-clocked generator to adjust the processing delay (latency) needed/allowed to the processing cycle in the circuit/system. The timing of the self-clocked generator is dynamically adjustable depending on various parameters. These parameters may include processing instruction, opcode information, type of processing to be performed by the circuit/system, or overall desired processing performance. The latency may also be adjusted to change processing performance, including power consumption, speed etc.

Abstract: A clock-less asynchronous processing circuit or system having a plurality of pipelined processing stages utilizes self-clocked generators to tune the delay needed in each of the processing stages to complete the processing cycle. Because different processing stages may require different amounts of time to complete processing or may require different delays depending on the processing required in a particular stage, the self-clocked generators may be tuned to each stage's necessary delay(s) or may be programmably configured.

Abstract: Embodiments are provided for an asynchronous processor with a Hierarchical Token System. The asynchronous processor includes a set of primary processing units configured to gate and pass a set of tokens in a predefined order of a primary token system. The asynchronous processor further includes a set of secondary units configured to gate and pass a second set of tokens in a second predefined order of a secondary token system. The set of tokens of the primary token system includes a token consumed in the set of primary processing units and designated for triggering the secondary token system in the set of secondary units.

Abstract: A clock-less asynchronous processing circuit or system is configured to operation in a plurality of modes. In an initialization mode (e.g., reset, initialization, boot up), a self-clocked generator associated with the asynchronous circuit is configured to generate an active complete signal (to latch output processed data) within a first period of time after receiving a trigger signal. In a normal mode, the self-clocked generator is configured to generate the active complete signal within a second period of time after receiving the trigger signal. In one embodiment, during the initialization mode, the asynchronous circuit latches the output slower than when in the normal mode.

Abstract: Embodiments are provided for adding a token jump logic to an asynchronous processor with token passing. The token jump logic allows token forward jumps and token backward jumps over a cascade of token processing logics in the processor. An embodiment method includes determining, using a token jump logic coupled to a cascade of token processing logics, whether to administer a token forward jump or a token backward jump of a token signal passing through the token processing logics. The token forward jump and token backward jump allow the token signal to skip one or more token processing logics in the cascade. The method further includes monitoring, for each of the token processing logics, a polarity status of a token sense logic, and inverting the polarity status according to the determination at the token jump logic.