Patents by Inventor Qifeng Cai

Qifeng Cai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10636779
    Abstract: The present disclosure provides a packaging device for an integrated power supply system and a packaging method thereof. The packaging device comprises: a power consumption system die and a power supply system die below the power consumption system die; the power supply system die comprises an active module, a passive module and a rewiring layer, wherein the active module and the reactive module are molded, and the rewiring layer is located above the molded active module and passive module, to connect the active module and the passive module, and a plurality of power supply tracks are disposed in the rewiring layer to abut the power consumption system die; the power consumption system die is abutted with the plurality of power supply tracks; and an external power source supplies power to the power consumption system die through the power supply system die.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: April 28, 2020
    Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
    Inventors: Jangshen Lin, Chengchung Lin, Chihhung Ho, Qifeng Cai
  • Publication number: 20190043846
    Abstract: The present disclosure provides a packaging device for an integrated power supply system and a packaging method thereof. The packaging device comprises: a power consumption system die and a power supply system die below the power consumption system die; the power supply system die comprises an active module, a passive module and a rewiring layer, wherein the active module and the reactive module are molded, and the rewiring layer is located above the molded active module and passive module, to connect the active module and the passive module, and a plurality of power supply tracks are disposed in the rewiring layer to abut the power consumption system die; the power consumption system die is abutted with the plurality of power supply tracks; and an external power source supplies power to the power consumption system die through the power supply system die.
    Type: Application
    Filed: August 1, 2017
    Publication date: February 7, 2019
    Inventors: Changshen LIN, Chengchung LIN, Chihhung HO, Qifeng CAI
  • Patent number: 10056350
    Abstract: The method of fabricating a fan-out package structure comprises: S1, providing a substrate (1), forming an adhesive layer (2) on the substrate's upper surface; S2, forming a redistribution layer (3) on the adhesive layer's upper surface; S3, bonding one first chip (4) to the redistribution layer's upper surface, and constructing at least two first bump structures (5), wherein the first chip and the first bump structures are all electrically connected to the redistribution layer, and top portions of the first bump structures are taller than a top portion of the first chip; S4, forming a plastic encapsulation layer (6) on the upper surface of the redistribution layer, wherein the plastic encapsulation layer embeds the first chip and exposes upper ends of the first bump structures; and S5, removing the substrate and the adhesive layer, and constructing a second bump structure (7) on a lower surface of the redistribution layer.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: August 21, 2018
    Assignee: SJ Semiconductor (Jiangyin) Corporation
    Inventors: Chengchung Lin, Qifeng Cai
  • Publication number: 20180158798
    Abstract: The method of fabricating a fan-out package structure comprises: S1, providing a substrate (1), forming an adhesive layer (2) on the substrate's upper surface; S2, forming a redistribution layer (3) on the adhesive layer's upper surface; S3, bonding one first chip (4) to the redistribution layer's upper surface, and constructing at least two first bump structures (5), wherein the first chip and the first bump structures are all electrically connected to the redistribution layer, and top portions of the first bump structures are taller than a top portion of the first chip; S4, forming a plastic encapsulation layer (6) on the upper surface of the redistribution layer, wherein the plastic encapsulation layer embeds the first chip and exposes upper ends of the first bump structures; and S5, removing the substrate and the adhesive layer, and constructing a second bump structure (7) on a lower surface of the redistribution layer.
    Type: Application
    Filed: March 14, 2016
    Publication date: June 7, 2018
    Inventors: Chengchung LIN, Qifeng CAI
  • Publication number: 20040091939
    Abstract: A device is provided for the detection of multiple analytes in at least one sample. The device contains a solid substrate with a test surface. On the test surface is defined at least one reaction area containing at least one array of discrete test sites. Each of these test sites have a test molecule immobilized on to it, and different test sites may have different test molecules immobilized thereon. A divider is provided for attachment onto the solid substrate. The divider contains a plurality of holes provided on an attachment surface. The attachment surface is complementary to the test surface of the solid device and is adapted for reversible attachment thereto such that when the two parts are attached, each of the holes is adjoined with a portion of the test surface to create a plurality of leak-proof chambers. The test surface within the chamber contains a plurality of test sites exposed within the chambers.
    Type: Application
    Filed: September 23, 2003
    Publication date: May 13, 2004
    Inventors: To Cheung, Bin Li, Yongji Peng, Yiping Ren, Haipeng Ge, Fuqiao Deng, Li Ding, Hongmei Li, Qifeng Cai, Ying Chen