Abstract: Systems and methods for a controller including controller memory and logic are presented herein. The logic is configured to control access to a persistent storage media and, in response to one or more commands, the logic determines an intermediate parity value based on a first parity calculation, and using the intermediate parity value determines a final parity value based on the intermediate parity value and a second parity calculation. Determining the intermediate parity value includes sending a uni-directional command to read an old data value from an address indicated in the uni-directional command, perform an exclusive-or operation on the old data value and a new data value indicated in the uni-directional command to determine the intermediate parity value and store, in the persistent storage media, the intermediate parity value at a location associated to an index indicated in the uni-directional command.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control local access to a persistent storage media and, in response to one or more commands, to determine an intermediate parity value based on a first local parity calculation, locally store the intermediate parity value, and determine a final parity value based on the intermediate parity value and a second local parity calculation. Other embodiments are disclosed and claimed.

Abstract: Technologies for adaptive processing of multiple buffers is disclosed. A compute device may establish a buffer queue to which applications can submit buffers to be processed, such as by hashing the submitted buffers. The compute device monitors the buffer queue and determines an efficient way of processing the buffer queue based on the number of buffers present. The compute device may process the buffers serially with a single processor core of the compute device or may process the buffers in parallel with single-instruction, multiple data (SIMD) instructions. The compute device may determine which method to use based on a comparison of the throughput of serially processing the buffers as compared to parallel processing the buffers, which may depend on the number of buffers in the buffer queue.

Abstract: Technologies for adaptive processing of multiple buffers is disclosed. A compute device may establish a buffer queue to which applications can submit buffers to be processed, such as by hashing the submitted buffers. The compute device monitors the buffer queue and determines an efficient way of processing the buffer queue based on the number of buffers present. The compute device may process the buffers serially with a single processor core of the compute device or may process the buffers in parallel with single-instruction, multiple data (SIMD) instructions. The compute device may determine which method to use based on a comparison of the throughput of serially processing the buffers as compared to parallel processing the buffers, which may depend on the number of buffers in the buffer queue.