Abstract: A circuit includes an ATX power connector with a PSON pin, a time delay circuit, and a stabilizer circuit. The time delay circuit receives an input PSON# signal and then sends an output PSON# signal to the PSON pin of the power connector after a time delay has elapsed. The stabilizer circuit is coupled to the PSON pin of the power connector for stabilizing the output PSON# signal.

Abstract: A circuit for confirming a correct computer power down sequence includes a Southbridge chip, a first switching transistor circuit, and a second switching transistor circuit. The first switching transistor circuit receives a power good signal. The second switching transistor circuit receives a S3 sleep signal. The first and second switching transistor circuits have a common output node coupled to the Southbridge chip. During a computer power down sequence, the S3 sleep signal is set from high to low before than the power good signal, and the S3 sleep signal is active and fed to the Southbridge chip, thereby quickly providing a low level power good signal to the Southbridge chip and confirming the power down sequence is correct.

Abstract: A computer wake up circuit includes a first control circuit and a second control circuit. The first control circuit has an input terminal configured to receive a first control signal from a first serial device, and an output terminal coupled to a south bridge which is capable of waking up a computer. The second control circuit has an input terminal respectively coupled to a second serial device and an I/O controller, and an output terminal coupled to the south bridge. The second control circuit receives a second control signal from the second serial device. The first and second control circuits respectively outputs a wake up signal to the south bridge to wake up the computer according to the control signals. The I/O controller communicates with the second serial device through the second control circuit, and outputs other control signals to control operations of the second serial device.

Abstract: A circuit for a computer system, includes a pulse width module (PWM) module and a control circuit. The PWM module is capable of converting a first voltage to a second voltage. The first voltage is capable of decreasing slower than the second voltage to have the PWM module entering in an unwanted state when the computer system is changed from a first state to a second state. The PWM module includes a disabling pin capable of locking the PWM module when a voltage of the disabling pin is low. The control circuit includes a control pin connected to the disabling pin, a ground pin connected to ground, and a monitoring pin capable of monitoring the computer system being changed from a first state to a second state to control the control pin and the ground pin to pull the disabling pin low to lock the PWM module to prevent the PWM module from entering in the unwanted state.

Abstract: A circuit for confirming a correct computer power down sequence includes a Southbridge chip, a first switching transistor circuit, and a second switching transistor circuit. The first switching transistor circuit receives a power good signal. The second switching transistor circuit receives a S3 sleep signal. The first and second switching transistor circuits have a common output node coupled to the Southbridge chip. During a computer power down sequence, the S3 sleep signal is set from high to low before than the power good signal, and the S3 sleep signal is active and fed to the Southbridge chip, thereby quickly providing a low level power good signal to the Southbridge chip and confirming the power down sequence is correct.

Abstract: A motherboard includes a printed circuit board, and a heat generating component mounted on the printed circuit board. A plurality of mounting holes is defined in the printed circuit board for mounting a heat sink apparatus on the heat generating component. At least a ground via is defined in the printed circuit board and adjacent to each of the mounting holes. The heat sink apparatus is capable of electrically contacting the ground via, and the ground via is capable of reducing electromagnetic interference of the motherboard and grounding static electricity on the heat sink apparatus.

Abstract: A computer wake up circuit includes a first control circuit and a second control circuit. The first control circuit has an input terminal configured to receive a first control signal from a first serial device, and an output terminal coupled to a south bridge which is capable of waking up a computer. The second control circuit has an input terminal respectively coupled to a second serial device and an I/O controller, and an output terminal coupled to the south bridge. The second control circuit receives a second control signal from the second serial device. The first and second control circuits respectively outputs a wake up signal to the south bridge to wake up the computer according to the control signals. The I/O controller communicates with the second serial device through the second control circuit, and outputs other control signals to control operations of the second serial device.

Abstract: A multi-layer printed circuit board includes a first trace layer and a second trace layer. The second trace layer and the first trace layer are located on parallel horizontal planes. A first group of traces is laid on the first trace layer. A second group of traces is laid on the second trace layer. The second group of traces and the first group of traces are positioned on up and down positions of the first trace layer and the second trace layer. The first group of traces and the second group of traces extend in different directions.

Abstract: A circuit includes an ATX power connector with a PSON pin, a time delay circuit, and a stabilizer circuit. The time delay circuit receives an input PSON# signal and then sends an output PSON# signal to the PSON pin of the power connector after a time delay has elapsed. The stabilizer circuit is coupled to the PSON pin of the power connector for stabilizing the output PSON# signal.

Abstract: A circuit for a computer system, includes a pulse width module (PWM) module and a control circuit. The PWM module is capable of converting a first voltage to a second voltage. The first voltage is capable of decreasing slower than the second voltage to have the PWM module entering in an unwanted state when the computer system is changed from a first state to a second state. The PWM module includes a disabling pin capable of locking the PWM module when a voltage of the disabling pin is low. The control circuit includes a control pin connected to the disabling pin, a ground pin connected to ground, and a monitoring pin capable of monitoring the computer system being changed from a first state to a second state to control the control pin and the ground pin to pull the disabling pin low to lock the PWM module to prevent the PWM module from entering in the unwanted state.

Abstract: An assembly includes a circuit board (20) with a component attached thereon, a power supply (10) for providing power to the circuit board and the component separately, an ACPI chipset (65) for controlling the power supply, a protecting circuit (61) connected to the component, an I/O controller (64), and an enable circuit (62) for activating the I/O controller. The protecting circuit generates a protecting signal while the component is not connected properly to its power source. The I/O controller is responsive to the protecting signal to send a control signal to the ACPI chipset for shutting off the power supply.

Abstract: An assembly includes a circuit board (20) with a component attached thereon, a power supply (10) for providing power to the circuit board and the component separately, an ACPI chipset (65) for controlling the power supply, a protecting circuit (61) connected to the component, an I/O controller (64), and an enable circuit (62) for activating the I/O controller. The protecting circuit generates a protecting signal while the component is not connected properly to its power source. The I/O controller is responsive to the protecting signal to send a control signal to the ACPI chipset for shutting off the power supply.