Patents by Inventor Qimeng JIANG
Qimeng JIANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240113103Abstract: An integrated device, a semiconductor device, and an integrated device manufacturing method are provided, to improve capacitor integration density of the integrated device. The integrated device includes: A first dielectric layer is disposed on a first metal layer; the first metal layer, the first dielectric layer, and a gate metal layer on the first dielectric layer form a first capacitor; the gate metal layer, a second dielectric layer on the gate metal layer, and a second metal layer on the second dielectric layer form a second capacitor; and the first metal layer is connected to the second metal layer through a first conductor structure, so that the first capacitor and the second capacitor are connected in parallel.Type: ApplicationFiled: December 8, 2023Publication date: April 4, 2024Inventors: Gaofei TANG, Qilong BAO, Hanxing WANG, Qimeng JIANG, Dongfa OUYANG
-
Publication number: 20230420537Abstract: A field effect transistor includes a channel layer, a source, a drain, a gate structure, and a gate metal layer; and the gate structure includes a P-type gallium nitride layer and an N-type gallium nitride layer that are disposed in a stacking manner, so that a gate metal/pGaN Schottky diode is replaced with an nGaN/pGaN reverse bias diode, to improve a gate voltage-withstand capability of the field effect transistor, thereby improving a breakdown capability of the field effect transistor. A doping density of the P-type gallium nitride layer is between 1×1018 cm?3 and 1×1019 cm?3, so that a charge storage effect during operation of a device can be reduced, carriers at the pGaN layer can be exhausted as much as possible, and redundant-charge storage is avoided, thereby improving operating threshold voltage stability of the device.Type: ApplicationFiled: September 8, 2023Publication date: December 28, 2023Inventors: Qilong BAO, Qimeng JIANG, Gaofei TANG, Hanxing WANG, Gilberto CURATOLA
-
Publication number: 20230411486Abstract: The disclosure relates to a Gallium Nitride power transistor, comprising: a buffer layer; and a barrier layer having a top side, a bottom side, the bottom side facing the buffer layer, the bottom side of the barrier layer is placed on the buffer layer; an interlayer interposed between a p-type doped Gallium Nitride layer and a metal gate layer, the interlayer is made of a III-V compound semiconductor comprising a combination of at least one group III element with at least one group V element, the p-type doped Gallium Nitride layer is placed on the top side of the barrier layer, the metal gate layer is electrically connected to the p-type doped Gallium Nitride layer via the interlayer to form a rectifying metal-semiconductor junction with the p-type doped Gallium Nitride layer.Type: ApplicationFiled: September 1, 2023Publication date: December 21, 2023Inventors: Gilberto Curatola, Qilong Bao, Qimeng Jiang, Gaofei Tang, Hanxing Wang
-
Patent number: 11791627Abstract: An ESD protection circuit is provided, including a negative ESD protection module and a positive ESD protection module, where the negative ESD protection module includes a first resistor, a charging capacitor, a first field effect transistor, and a second field effect transistor, and the positive ESD protection module includes a fourth field effect transistor. When a negative ESD event occurs, there is a comparatively large transient voltage at a gate of a P-type enhanced GaN power device relative to a source of the P-type enhanced GaN power device. Therefore, a displacement current from the source to the gate of the P-type enhanced GaN power device is generated on the charging capacitor. A voltage drop generated by the displacement current on the first resistor may enable the first field effect transistor and the second field effect transistor to form a path when the first field effect transistor is turned on.Type: GrantFiled: July 12, 2022Date of Patent: October 17, 2023Assignee: Huawei Technologies Co., Ltd.Inventors: Qimeng Jiang, Yushan Li, Hanxing Wang
-
Patent number: 11705494Abstract: This application provides a gallium nitride component and a drive circuit thereof. The gallium nitride component includes: a substrate; a gallium nitride (GaN) buffer layer formed on the substrate; an aluminum gallium nitride (AlGaN) barrier layer formed on the GaN buffer layer; and a source, a drain, and a gate formed on the AlGaN barrier layer. The gate includes a P-doped gallium nitride (P—GaN) cap layer formed on the AlGaN barrier layer, and a first gate metal and a second gate metal formed on the P—GaN cap layer. A Schottky contact is formed between the first gate metal and the P—GaN cap layer, and an ohmic contact is formed between the second gate metal and the P—GaN cap layer. In the technical solution provided in this application, the gallium nitride component is a normally-off component, and is conducive to design of a drive circuit.Type: GrantFiled: March 15, 2022Date of Patent: July 18, 2023Assignee: Huawei Technologies Co., Ltd.Inventors: Boning Huang, Zhaozheng Hou, Qimeng Jiang
-
Publication number: 20230187523Abstract: This application provides a hybrid gate field effect transistor, a method for preparing the hybrid gate field effect transistor, and a switch circuit. The hybrid gate field effect transistor includes a channel layer, and a source, a drain, and a gate structure disposed on the channel layer. The gate structure is a hybrid gate structure prepared from two materials. The gate structure includes a first structural layer and a second structural layer. The second structural layer wraps the first structural layer. The first structural layer is an N-type gallium nitride layer or an intrinsic gallium nitride layer; and the second structural layer is a P-type gallium nitride layer. The gate metal layer is disposed on one side of the gate structure facing away from the channel layer, and the gate metal layer is in ohmic contact with the first structural layer.Type: ApplicationFiled: February 8, 2023Publication date: June 15, 2023Inventors: Ruihong LUO, Boning HUANG, Hui SUN, Qimeng JIANG, Qilong BAO, Zhibin CHEN
-
Publication number: 20230006440Abstract: An ESD protection circuit is provided, including a negative ESD protection module and a positive ESD protection module, where the negative ESD protection module includes a first resistor, a charging capacitor, a first field effect transistor, and a second field effect transistor, and the positive ESD protection module includes a fourth field effect transistor. When a negative ESD event occurs, there is a comparatively large transient voltage at a gate of a P-type enhanced GaN power device relative to a source of the P-type enhanced GaN power device. Therefore, a displacement current from the source to the gate of the P-type enhanced GaN power device is generated on the charging capacitor. A voltage drop generated by the displacement current on the first resistor may enable the first field effect transistor and the second field effect transistor to form a path when the first field effect transistor is turned on.Type: ApplicationFiled: July 12, 2022Publication date: January 5, 2023Inventors: Qimeng JIANG, Yushan LI, Hanxing WANG
-
Patent number: 11522527Abstract: This application discloses a chip and a signal level shifter circuit for use on a mobile terminal such as a charger or an adapter. The chip is co-packaged with a first silicon-based driver die and a second silicon-based driver die that are manufactured by using a BCD technology, and a first gallium nitride die and a second gallium nitride die that are manufactured by using a gallium nitride technology. A first silicon-based circuit is integrated on the first silicon-based driver die, a second silicon-based circuit is integrated on the second silicon-based driver die, and a high-voltage resistant gallium nitride circuit is integrated on the first gallium nitride die. In this way, it can be ensured that a second low-voltage silicon-based driver die manufactured by using a low-voltage BCD technology is not damaged by a high input voltage, thereby reducing costs of the chip.Type: GrantFiled: September 7, 2021Date of Patent: December 6, 2022Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Qimeng Jiang, Xingqiang Peng, Chenghao Sun
-
Publication number: 20220344485Abstract: A gallium nitride (GaN) device, where a drain of the GaN device includes a p-type (P-GaN) layer and a drain metal. The drain metal includes a plurality of first structural intervals and a plurality of second structural intervals. The plurality of first structural intervals and the plurality of second structural intervals are alternately distributed in the gate width direction. In this way, the drain metal implements local injection of holes for the device in the first structural intervals, and forms ohmic contact in the second structural intervals, implementing current conduction from a drain to a source of the device.Type: ApplicationFiled: April 22, 2022Publication date: October 27, 2022Inventors: Qilong Bao, Qimeng Jiang, Gaofei Tang, Hanxing Wang, Boning Huang, Zhaozheng Hou
-
Patent number: 11411396Abstract: An ESD protection circuit is provided, including a negative ESD protection module and a positive ESD protection module, where the negative ESD protection module includes a first resistor, a charging capacitor, a first field effect transistor, and a second field effect transistor, and the positive ESD protection module includes a fourth field effect transistor. When a negative ESD event occurs, there is a comparatively large transient voltage at a gate of a P-type enhanced GaN power device relative to a source of the P-type enhanced GaN power device. Therefore, a displacement current from the source to the gate of the P-type enhanced GaN power device is generated on the charging capacitor. A voltage drop generated by the displacement current on the first resistor may enable the first field effect transistor and the second field effect transistor to form a path when the first field effect transistor is turned on.Type: GrantFiled: March 24, 2021Date of Patent: August 9, 2022Assignee: Huawei Technologies Co., Ltd.Inventors: Qimeng Jiang, Yushan Li, Hanxing Wang
-
Publication number: 20220199795Abstract: This application provides a gallium nitride component and a drive circuit thereof. The gallium nitride component includes: a substrate; a gallium nitride GaN buffer layer formed on the substrate; an aluminum gallium nitride AlGaN barrier layer formed on the GaN buffer layer; and a source, a drain, and a gate formed on the AlGaN barrier layer. The gate includes a P-doped gallium nitride P-GaN cap layer formed on the AlGaN barrier layer, and a first gate metal and a second gate metal formed on the P-GaN cap layer. A Schottky contact is formed between the first gate metal and the P-GaN cap layer, and an ohmic contact is formed between the second gate metal and the P-GaN cap layer. In the technical solution provided in this application, the gallium nitride component is a normally-off component, and is conducive to design of a drive circuit.Type: ApplicationFiled: March 15, 2022Publication date: June 23, 2022Inventors: Boning HUANG, Zhaozheng HOU, Qimeng JIANG
-
Publication number: 20210409005Abstract: This application discloses a chip and a signal level shifter circuit for use on a mobile terminal such as a charger or an adapter. The chip is co-packaged with a first silicon-based driver die and a second silicon-based driver die that are manufactured by using a BCD technology, and a first gallium nitride die and a second gallium nitride die that are manufactured by using a gallium nitride technology. A first silicon-based circuit is integrated on the first silicon-based driver die, a second silicon-based circuit is integrated on the second silicon-based driver die, and a high-voltage resistant gallium nitride circuit is integrated on the first gallium nitride die. In this way, it can be ensured that a second low-voltage silicon-based driver die manufactured by using a low-voltage BCD technology is not damaged by a high input voltage, thereby reducing costs of the chip.Type: ApplicationFiled: September 7, 2021Publication date: December 30, 2021Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Qimeng Jiang, Xingqiang Peng, Chenghao Sun
-
Publication number: 20210210955Abstract: An ESD protection circuit is provided, including a negative ESD protection module and a positive ESD protection module, where the negative ESD protection module includes a first resistor, a charging capacitor, a first field effect transistor, and a second field effect transistor, and the positive ESD protection module includes a fourth field effect transistor. When a negative ESD event occurs, there is a comparatively large transient voltage at a gate of a P-type enhanced GaN power device relative to a source of the P-type enhanced GaN power device. Therefore, a displacement current from the source to the gate of the P-type enhanced GaN power device is generated on the charging capacitor. A voltage drop generated by the displacement current on the first resistor may enable the first field effect transistor and the second field effect transistor to form a path when the first field effect transistor is turned on.Type: ApplicationFiled: March 24, 2021Publication date: July 8, 2021Inventors: Qimeng JIANG, Yushan LI, Hanxing WANG
-
Patent number: 9337028Abstract: Passivation of group III-nitride hetero junction devices is described herein. The passivation facilitates simultaneous realization of effective/high current collapse suppression and low leakage current without the use of a sophisticated multiple-field plate technique. The passivation can be achieved by growing a charge-polarized AlN thin film on the surface of a group III-nitride based heterojunction device by plasma-enhanced atomic layer deposition such that positive polarization charges are induced at the interface to compensate for a majority of negative charges at the interface.Type: GrantFiled: December 30, 2014Date of Patent: May 10, 2016Assignee: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Jing Chen, Sen Huang, Qimeng Jiang, Zhikai Tang
-
Publication number: 20150111371Abstract: Passivation of group III-nitride hetero junction devices is described herein. The passivation facilitates simultaneous realization of effective/high current collapse suppression and low leakage current without the use of a sophisticated multiple-field plate technique. The passivation can be achieved by growing a charge-polarized. AlN thin film on the surface of a group III-nitride based heterojunction device by plasma-enhanced atomic layer deposition such that positive polarization charges are induced at the interface to compensate for a majority of negative charges at the interface.Type: ApplicationFiled: December 30, 2014Publication date: April 23, 2015Inventors: Jing CHEN, Sen HUANG, Qimeng JIANG, Zhikai TANG
-
Patent number: 8937336Abstract: Passivation of group III-nitride heterojunction devices is described herein. The passivation facilitates simultaneous realization of effective/high current collapse suppression and low leakage current without the use of a sophisticated multiple-field plate technique. The passivation can be achieved by growing a charge-polarized AlN thin film on the surface of a group III-nitride based heterojunction device by plasma-enhanced atomic layer deposition such that positive polarization charges are induced at the interface to compensate for a majority of negative charges at the interface.Type: GrantFiled: May 16, 2013Date of Patent: January 20, 2015Assignee: The Hong Kong University of Science and TechnologyInventors: Jing Chen, Sen Huang, Qimeng Jiang, Zhikai Tang
-
Publication number: 20130306978Abstract: Passivation of group III-nitride heterojunction devices is described herein. The passivation facilitates simultaneous realization of effective/high current collapse suppression and low leakage current without the use of a sophisticated multiple-field plate technique. The passivation can be achieved by growing a charge-polarized AlN thin film on the surface of a group III-nitride based heterojunction device by plasma-enhanced atomic layer deposition such that positive polarization charges are induced at the interface to compensate for a majority of negative charges at the interface.Type: ApplicationFiled: May 16, 2013Publication date: November 21, 2013Applicant: The Hong Kong University of Science and TechnologyInventors: Jing CHEN, Sen HUANG, Qimeng JIANG, Zhikai TANG