Abstract: A transaction indicator monitoring computer-implemented method, medium, and system are disclosed. One computer-implemented method includes obtaining sampling sequences of a transaction indicator of transaction data under multiple sets of transaction dimension values, each set of transaction dimension values corresponding to one sampling sequence, a first sampling sequence including values of the transaction indicator at a predetermined quantity of sampling points under a first set of transaction dimension values, and a value of the transaction indicator at a target sampling point is a first actual value. An estimated value of the transaction indicator at the target sampling point in the first sampling sequence is calculated based on the first sampling sequence and compared with the first actual value, to determine whether the transaction indicator at the target sampling point under the first set of transaction dimension values corresponding to the first sampling sequence is abnormal.

Abstract: An intracranial thrombus removal apparatus includes a fretwork-type tube-shaped structure, and having a radially compressed loading state and a radially expanded released state. One end of the tube-shaped structure in an axial direction configured for connecting to a delivery is defined as a proximal end, and the other end in the axial direction closed by a mesh cover structure is defined as a distal end a mesh cover structure. The tube-shaped structure comprises a plurality of capturing claws, one end of each capturing claw is defined as a root part connected to a side wall of the tube-shaped structure, and the other end of each of the plurality of capturing claws is defined as a tip extending to an axis position of the tube-shaped structure, and each of the plurality of capturing claws inclines from the proximal end to the distal end while extending.

Abstract: A transaction indicator monitoring computer-implemented method, medium, and system are disclosed. One computer-implemented method includes obtaining sampling sequences of a transaction indicator of transaction data under multiple sets of transaction dimension values, each set of transaction dimension values corresponding to one sampling sequence, a first sampling sequence including values of the transaction indicator at a predetermined quantity of sampling points under a first set of transaction dimension values, and a value of the transaction indicator at a target sampling point is a first actual value. An estimated value of the transaction indicator at the target sampling point in the first sampling sequence is calculated based on the first sampling sequence and compared with the first actual value, to determine whether the transaction indicator at the target sampling point under the first set of transaction dimension values corresponding to the first sampling sequence is abnormal.

Abstract: A reference voltage circuit is disclosed that is independent of the voltage supply as well as substantially insensitive to process and temperature variations. The reference voltage circuit includes an intrinsic transistor circuit which includes a plurality of intrinsic transistors of equal size. The intrinsic transistor circuit is coupled to a current mirror circuit, and a plurality of threshold transistors. In so doing, a reference voltage circuit is provided that is substantially independent of process and temperature variations. In addition, by grounding the source connections of the plurality of threshold transistors, the reference voltage circuit output voltage also is substantially independent of supply voltage variations.

Abstract: A method for programming multiple values in an individual flash memory cell is disclosed. An individual flash cell is programmed by holding the bit line, corresponding to the particular memory cell to a value, V.sub.d, while the voltage on the control gate, V.sub.g, of the memory cell is varied. By varying the voltage on the control gate, multiple values are stored in the memory cell. The resulting values are self-convergent, therefore, verify circuitry becomes unnecessary.

Abstract: A flash memory device having a reduced area is disclosed. The device uses a polyI layer to act as a select transistor for the memory cells comprising the core array. Also, a ground plate is used to isolate the areas of the memory array where high voltage devices should not be located, thereby allowing peripheral components to be fabricated in the core array area. Also disclosed is a polyII layer used to access two sublines controlling two different sectors of the memory array architecture. By using such a layout, die space savings is attained.