Abstract: An image processing method is applied to an image processing circuit including a first application circuit and a second application circuit. The image processing circuit is coupled to a memory. The method includes the following steps: reading, by the first application circuit, a first image from the memory; processing, by the first application circuit, the first image to generate a part of a second image and progress information corresponding to the part; storing, by the first application circuit, the part of the second image in the memory; sending, by the first application circuit, the progress information; receiving, by the second application circuit, the progress information; reading, by the second application circuit, the part of the second image from the memory according to the progress information; and processing, by the second application circuit, the part of the second image.

Abstract: An image processing accelerator device includes a memory, a decoder circuit, an event monitor circuit and a filter control circuit. The memory receives a first command corresponding to a task, and a wait event command which follows the first command. The decoder circuit decodes the first command and the wait event command to determine a register to be accessed in an image processing circuit and first data to be written by the first command, and generates an event identifier. The event monitor circuit determines according to the event identifier whether the image processing circuit has finished executing the task, and accordingly controls the image processing circuit to execute a command corresponding to a next task. The filter control circuit records second data previously stored in the register, and writes the first data to the register when the first data is different from the second data.

Abstract: A data protection device includes a memory, a read-only memory and a verification circuit. The read-only memory stores first confidential data, and transmits the first confidential data to the memory after being powered up, wherein the first confidential data includes multiple groups of repetitive data and the groups of repetitive data are the same with one another. The verification data determines whether the first confidential data is valid before a processor reads the first confidential data from the memory, and allows the processor to read the first confidential data from the memory when the first confidential data is valid.

Abstract: An electronic device includes a memory and is coupled to an external storage device that stores a boot code of the electronic device. An operation method of the electronic device includes the following steps: (A) writing a first segment of the boot code into a memory block of the memory, (B) executing a part of the first segment of the boot code; and (C) executing a target code in the memory block in response to an interrupt.

Abstract: A media access control (MAC) circuit is coupled to a physical layer circuit and includes a storage circuit, a receiving circuit, a checking circuit, and a protection circuit. The storage circuit is configured to store a first value and a second value. The receiving circuit is configured to receive a packet from the physical layer circuit. The checking circuit is configured to check the packet. The protection circuit is configured to perform the following steps: updating the first value according to a clock; and discarding the packet when the absolute difference between the first value and a reference value is smaller than the second value.

Abstract: An electronic device and a control method thereof are provided. The electronic device includes a read-only memory (ROM) that stores a first characteristic value of a public key. The control method includes the following steps: reading the public key and a plurality of boot codes of the electronic device from an external storage device; executing the boot codes; and verifying the public key according to the first characteristic value. The public key is used to verify the boot codes, and the number of bits of the first characteristic value is smaller than the number of bits of the public key. The ROM is disposed on a first chip, and the external storage device is disposed on a second chip.

Abstract: A data transmission control device is provided. The data transmission control device is disposed in a chip that includes a Peripheral Component Interconnect Express (PCIe) interface, and the data transmission control device is coupled to a memory that includes a block. The data transmission control device includes: a control circuit, a PCIe interface controller, and an address monitoring circuit. The PCIe interface controller is configured to receive a data. The address monitoring circuit is configured to issue an interrupt to the control circuit when the data is written to the block.