Abstract: A programmable logic device, in accordance with one embodiment, includes a plurality of configuration memory cells, wherein at least one configuration memory cell is adapted to function as random access memory. Read/write circuitry writes to and reads from a corresponding first port of the configuration memory cells, including reading from the at least one configuration memory cell adapted to function as random access memory. Soft error detection logic checks for an error in data values stored by the plurality of configuration memory cells, including the at least one configuration memory cell adapted to function as random access memory. The soft error detection logic, for example, may thus be tested by changing a data value stored in the at least one configuration memory cell.

Abstract: Systems and methods are disclosed herein to provide high fan-out signal routing. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks; an interconnect structure adapted to route signals among the logic blocks; and a secondary routing network adapted to route signals among the logic blocks. The secondary routing network may include a plurality of horizontal splines adapted to route signals within the programmable logic device; a plurality of vertical spline taps adapted to route signals within the programmable logic device; a plurality of common interface blocks adapted to route signals between the horizontal splines and the vertical spline taps; and a plurality of horizontal secondary branches adapted to route signals from the vertical spline taps to the logic blocks.