Patents by Inventor Qing A. Zhou

Qing A. Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8189361
    Abstract: Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die on the other substrate. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: May 29, 2012
    Assignee: Intel Corporation
    Inventors: Qing A. Zhou, Daoqiang Lu, Jiangqi He, Wei Shi, Xiang Yin Zeng
  • Patent number: 8012808
    Abstract: Some embodiments of the present invention include apparatuses and methods relating to integrated micro-channels for removing heat from 3D through silicon architectures.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: September 6, 2011
    Assignee: Intel Corporation
    Inventors: Wei Shi, Daoqiang Lu, Yiqun Bai, Qing A. Zhou, Jianqqi He
  • Publication number: 20110058419
    Abstract: Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die on the other substrate. Other embodiments are described and claimed.
    Type: Application
    Filed: November 3, 2010
    Publication date: March 10, 2011
    Inventors: Qing A. Zhou, Daoqiang Lu, Jiangqi He, Wei Shi, Xiang Yin Zeng
  • Patent number: 7851809
    Abstract: Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die on the other substrate. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: December 14, 2010
    Assignee: Intel Corporation
    Inventors: Qing A. Zhou, Daoqiang Lu, Jiangqi He, Wei Shi, Xiang Yin Zeng
  • Publication number: 20090250707
    Abstract: Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die on the other substrate. Other embodiments are described and claimed.
    Type: Application
    Filed: June 12, 2009
    Publication date: October 8, 2009
    Inventors: Qing A. Zhou, Daoqiang Lu, Jianggi He, Wei Shi, Xiang Yin Zeng
  • Publication number: 20090201643
    Abstract: Some embodiments of the present invention include apparatuses and methods relating to integrated micro-channels for removing heat from 3D through silicon architectures.
    Type: Application
    Filed: February 8, 2008
    Publication date: August 13, 2009
    Inventors: Wei Shi, Daoqiang Lu, Yiqun Bai, Qing A. Zhou, Jianqqi He
  • Patent number: 7564066
    Abstract: Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die on the other substrate. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: July 21, 2009
    Assignee: Intel Corporation
    Inventors: Qing A. Zhou, Daoqiang Lu, Jiangqi He, Wei Shi, Xiang Yin Zeng
  • Patent number: 7554203
    Abstract: An integrated circuit (“IC”) package having two or more dice stacked on a substrate and electrically coupled using two or more different connection technologies may improve high-speed input/output (“I/O”) bandwidth. In an embodiment, one die is a processor and at least one other die is a dynamic random access memory (“DRAM”). One or more of the dice may be thinned and placed between the substrate and a portion of one or more of the other dice, which may be horizontally offset. One or more of the dice may be embedded in the substrate. The dice may be coupled to each other and to the substrate using a combination of controlled-collapse chip connection (“C4”) and wirebonding connection technologies. Methods of fabrication, and application of the package to an electronic assembly and to an electronic system, are also described.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: June 30, 2009
    Assignee: Intel Corporation
    Inventors: Qing A Zhou, Daoqiang Lu, Wei Shi, Jiangqi He
  • Patent number: 7432592
    Abstract: Some embodiments of the present invention include apparatuses and methods relating to integrated micro-channels for removing heat from 3D through silicon architectures.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: October 7, 2008
    Assignee: Intel Corporation
    Inventors: Wei Shi, Daoqiang Lu, Yiqun Bai, Qing A. Zhou, Jiangqi He
  • Patent number: 7348678
    Abstract: A system may include a microprocessor die, an integrated circuit package substrate, and a die disposed between the microprocessor die and the integrated circuit package substrate. In some embodiments, the integrated circuit package substrate defines a first cavity, and the die is disposed at least partially within the first cavity.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventors: Qing A. Zhou, Wei O. Shi, Jiangqi He, Daoqiang Lu
  • Publication number: 20080003717
    Abstract: An integrated circuit (“IC”) package having two or more dice stacked on a substrate and electrically coupled using two or more different connection technologies may improve high-speed input/output (“I/O”) bandwidth. In an embodiment, one die is a processor and at least one other die is a dynamic random access memory (“DRAM”). One or more of the dice may be thinned and placed between the substrate and a portion of one or more of the other dice, which may be horizontally offset. One or more of the dice may be embedded in the substrate. The dice may be coupled to each other and to the substrate using a combination of controlled-collapse chip connection (“C4”) and wirebonding connection technologies. Methods of fabrication, and application of the package to an electronic assembly and to an electronic system, are also described.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Qing A. Zhou, Daoqiang Lu, Wei Shi, Jiangqi He