Abstract: Systems and methods for on-chip resistor calibration are disclosed. A circuit for calibrating a resistance value on an integrated circuit includes a resistor network, a reference voltage generator, a comparator, a servo loop, and a shift register. The resistor network includes a plurality of resistor and switch pairs in parallel. The resistor network further includes a servo resistor in series with a servo resistor switch such that the servo resistor and servo resistor switch are in parallel with the plurality of resistor and switch pairs. The servo loop generates a shift register gating signal and includes a current sample register for storing a current comparator output data value and a previous sample register for storing a previous comparator output data value. The shift register, upon receipt of a shift register gating signal at a first state, inputs the current comparator output data value to shift data bits through the shift register.

Abstract: A voltage/current reference circuit includes a first bipolar transistor and a second bipolar transistor that exhibit a first voltage drop VBE1 and a second voltage drop VBE2, respectively. A first resistor, having a resistance R1, is configured to draw a first current equal to (VBE1?VBE2)/R1. A second resistor, having a resistance R2, is configured to draw a second current equal to VBE1/R2. A first transistor supplies the first and second currents to the first and second resistors. A second transistor, having a current mirror configuration with respect to the first transistor, directly provides a reference current equal to (VBE1?VBE2)/R1+VBE1/R2. A third transistor, having a current mirror configuration with respect to the first transistor, provides a current equal to the reference current to a third resistor having a resistance R3 and a third bipolar transistor that exhibits a third voltage drop VBE3, thereby generating a reference voltage.

Abstract: A voltage/current reference circuit includes a first bipolar transistor and a second bipolar transistor that exhibit a first voltage drop VBE1 and a second voltage drop VBE2, respectively. A first resistor, having a resistance R1, is configured to draw a first current equal to (VBE1?VBE2)/R1. A second resistor, having a resistance R2, is configured to draw a second current equal to VBE1/R2. A first transistor supplies the first and second currents to the first and second resistors. A second transistor, having a current mirror configuration with respect to the first transistor, directly provides a reference current equal to (VBE1?VBE2)/R1+VBE1/R2. A third transistor, having a current mirror configuration with respect to the first transistor, provides a current equal to the reference current to a third resistor having a resistance R3 and a third bipolar transistor that exhibits a third voltage drop VBE3, thereby generating a reference voltage.