Abstract: A charge pump device with NMOS transistor circuit is provided for low voltage operation. The charge pump stage, comprising four NMOS transistors and three capacitors, is configured to alleviate the substrate body effect and the charge transfer loss. The charge pump circuit can be constructed on a p-type semiconductor substrate directly without deep N well isolation. The circuit is driven by two non-overlapping complementary clock signals, which can be generated easily with an integrated fabrication. The charge pump device can be implemented with a multiple stage to provide a stable high voltage output.

Abstract: A memory device comprises at least one memory array on a semiconductor substrate. Each said memory array comprises a page control line and a plurality of pages, each said page is arranged in a row comprising a plurality of bytes which couple to a page control transistor with its drain terminal connected to the page control line. Each said byte includes at least one memory cell. Said memory array further comprises a plurality of source control devices which are configured to provide either predetermined biases or floating potentials to source lines, each said source line couples to all the bytes on the same byte segment of the memory array. Read, erase, and program methods are provided to operate said memory devices in byte addressable fashion.

Abstract: A memory device comprises at least one memory array on a semiconductor substrate. Each said memory array comprises a page control line and a plurality of pages, each said page is arranged in a row comprising a plurality of bytes which couple to a page control transistor with its drain terminal connected to the page control line. Each said byte includes at least one memory cell. Said memory array further comprises a plurality of source control devices which are configured to provide either predetermined biases or floating potentials to source lines, each said source line couples to all the bytes on the same byte segment of the memory array. Read, erase, and program methods are provided to operate said memory devices in byte addressable fashion.