Patents by Inventor Qingcheng WANG
Qingcheng WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11494192Abstract: A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.Type: GrantFiled: April 28, 2020Date of Patent: November 8, 2022Assignees: Advanced Micro Devices, Inc., ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD.Inventors: Jiasheng Chen, YunXiao Zou, Bin He, Angel E. Socarras, QingCheng Wang, Wei Yuan, Michael Mantor
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Patent number: 11347827Abstract: Systems, apparatuses, and methods implementing a hybrid matrix multiplication pipeline are disclosed. A hybrid matrix multiplication pipeline is able to execute a plurality of different types of instructions in a plurality of different formats by reusing execution circuitry in an efficient manner. For a first type of instruction for source operand elements of a first size, the pipeline uses N multipliers to perform N multiplication operations on N different sets of operands, where N is a positive integer greater than one. For a second type of instruction for source operand elements of a second size, the N multipliers work in combination to perform a single multiplication operation on a single set of operands, where the second size is greater than the first size. The pipeline also shifts element product results in an efficient manner when implementing a dot product operation.Type: GrantFiled: February 27, 2019Date of Patent: May 31, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Jiasheng Chen, Qingcheng Wang, Yunxiao Zou
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Publication number: 20200293329Abstract: A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.Type: ApplicationFiled: April 28, 2020Publication date: September 17, 2020Inventors: Jiasheng CHEN, YunXiao ZOU, Bin HE, Angel E. SOCARRAS, QingCheng WANG, Wei YUAN, Michael MANTOR
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Publication number: 20200272687Abstract: Systems, apparatuses, and methods implementing a hybrid matrix multiplication pipeline are disclosed. A hybrid matrix multiplication pipeline is able to execute a plurality of different types of instructions in a plurality of different formats by reusing execution circuitry in an efficient manner. For a first type of instruction for source operand elements of a first size, the pipeline uses N multipliers to perform N multiplication operations on N different sets of operands, where N is a positive integer greater than one. For a second type of instruction for source operand elements of a second size, the N multipliers work in combination to perform a single multiplication operation on a single set of operands, where the second size is greater than the first size. The pipeline also shifts element product results in an efficient manner when implementing a dot product operation.Type: ApplicationFiled: February 27, 2019Publication date: August 27, 2020Inventors: Jiasheng Chen, Qingcheng Wang, Yunxiao Zou
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Patent number: 10656951Abstract: A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.Type: GrantFiled: October 20, 2017Date of Patent: May 19, 2020Assignees: ADVANCED MICRO DEVICES, INC., ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD.Inventors: Jiasheng Chen, YunXiao Zou, Bin He, Angel E. Socarras, QingCheng Wang, Wei Yuan, Michael Mantor
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Patent number: 10360177Abstract: Described is a method and processing apparatus to improve power efficiency by gating redundant threads processing. In particular, the method for gating redundant threads in a graphics processor includes determining if data for a thread and data for at least another thread are within a predetermined similarity threshold, gating execution of the at least another thread if the data for the thread and the data for the at least another thread are within the predetermined similarity threshold, and using an output data from the thread as an output data for the at least another thread.Type: GrantFiled: June 22, 2016Date of Patent: July 23, 2019Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Syed Zohaib M. Gilani, Jiasheng Chen, QingCheng Wang, YunXiao Zou, Michael Mantor, Bin He, Timour T. Paltashev
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Publication number: 20190004807Abstract: Systems, apparatuses, and methods for implementing a stream processor with overlapping execution are disclosed. In one embodiment, a system includes at least a parallel processing unit with a plurality of execution pipelines. The processing throughput of the parallel processing unit is increased by overlapping execution of multi-pass instructions with single pass instructions without increasing the instruction issue rate. A first plurality of operands of a first vector instruction are read from a shared vector register file in a single clock cycle and stored in temporary storage. The first plurality of operands are accessed and utilized to initiate multiple instructions on individual vector elements on a first execution pipeline in subsequent clock cycles. A second plurality of operands are read from the shared vector register file during the subsequent clock cycles to initiate execution of one or more second vector instructions on the second execution pipeline.Type: ApplicationFiled: July 24, 2017Publication date: January 3, 2019Inventors: Jiasheng Chen, Qingcheng Wang, Yunxiao Zou, Bin He, Jian Yang, Michael J. Mantor, Brian D. Emberling
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Publication number: 20180113714Abstract: A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.Type: ApplicationFiled: October 20, 2017Publication date: April 26, 2018Inventors: Jiasheng CHEN, YunXiao ZOU, Bin HE, Angel E. SOCARRAS, QingCheng WANG, Wei YUAN, Michael MANTOR
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Publication number: 20170371393Abstract: Described is a method and processing apparatus to improve power efficiency by gating redundant threads processing. In particular, the method for gating redundant threads in a graphics processor includes determining if data for a thread and data for at least another thread are within a predetermined similarity threshold, gating execution of the at least another thread if the data for the thread and the data for the at least another thread are within the predetermined similarity threshold, and using an output data from the thread as an output data for the at least another thread.Type: ApplicationFiled: June 22, 2016Publication date: December 28, 2017Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Syed Zohaib M. Gilani, Jiasheng Chen, QingCheng Wang, YunXiao Zou, Michael Mantor, Bin He, Timour T. Paltashev
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Patent number: 8986683Abstract: The invention discloses a kit which comprises a formulation containing artemisinin or the derivatives thereof, a formulation containing ribonuclease, and a specification.Type: GrantFiled: September 10, 2012Date of Patent: March 24, 2015Assignees: Shanghai Biomodel Organism Science & Technology Co., Ltd., Shanghai Research Center for Model OrganismsInventors: Qingcheng Wang, Ruling Shen, Jun Li, Jian Fei, Zhugang Wang
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Publication number: 20130052181Abstract: The invention discloses a kit which comprises a formulation containing artemisinin or the derivatives thereof, a formulation containing ribonuclease, and a specification.Type: ApplicationFiled: September 10, 2012Publication date: February 28, 2013Applicants: Shanghai Research Center for Model Organisms, Shanghai Biomodel Organism Science & Technology Development Co., Ltd.Inventors: Qingcheng WANG, Ruling SHEN, Jun LI, Jian FEI, Zhugang WANG