Abstract: The method of forming the semiconductor structure comprises operations of: forming a substrate, and forming active regions located above the substrate and arranged at intervals in a first direction parallel to a top face of the substrate; and performing a modifying treatment to a part of the substrate below the active regions from at least one side face of the substrate, to form bit lines each of which extends in the first direction and is electrically connected with a plurality of the active regions arranged at intervals in the first direction

Abstract: It discloses a sustained release grouting material, a preparation method and an application thereof; the sustained release grouting material comprises a water swelling core and a water-soluble sustained release coating, the water swelling core is composed of bentonite, SAP and xanthan gum, which is granulated by disc granulator relying on the cohesiveness of xanthan gum; the water-soluble sustained-release coating is prepared by mixing water-soluble starch, polyvinyl alcohol, poloxamer, lubricant and plasticizer with deionized water to obtain a film-forming solution, and the film-forming solution is coated on a coating machine; the invention uses a coating machine to coat a layer of slow-release coating on the surface of the water-absorbing expansion core, and adjusts the coating thickness by controlling the mass ratio of the coating film-forming liquid to the water-absorbing expansion core particles, so as to realize the controllable water absorption onset time of the expansion core.

Abstract: The application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate and multiple Word Lines (WLs), the multiple WLs extend along a first direction and are arranged on the substrate at intervals along a second direction, a WL isolation structure is arranged between every two adjacent WLs and includes at least a first isolation layer and a second isolation layer stacked along the second direction and made of different materials, and the first direction and the second direction intersect with each other.

Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The manufacturing method includes the following operations. A substrate is provided, and a first groove and a second groove are formed in the substrate, each of the first groove and the second groove having a depth in a first direction. The first groove includes multiple first sub-grooves arranged in the first direction, the second groove includes multiple second sub-grooves arranged in the first direction, and sidewalls of the first sub-grooves and sidewalls of the second sub-grooves are convex outwards. Word lines protruding away from the first groove each are formed at an interface of adjacent first sub-grooves. First source-drain layers formed on the sidewalls of the first sub-grooves, and second source-drain layers protruding away from the second groove each are formed at an interface of adjacent second sub-grooves.

Abstract: The present disclosure provides a semiconductor structure including: a channel on a semiconductor substrate for a first transistor; first bit lines are in contact with the first doped region arranged along the first direction; first word lines surround the channel region; the gate conductive layer and the second doped region, the channel layer arranged around the outer side of the gate conductive layer; the first semiconductor doped layer and the second semiconductor doped layer arranged on the outer side of the channel layer, so the channel layer and the gate conductive layer constitute the second transistor. The second bit line is in contact with either the first semiconductor doped layer or the second semiconductor doped layer; the second word line is in contact with the other one of the first semiconductor or the second semiconductor doped layer. The structure forms a new 2T0C DRAM structure.

Abstract: A semiconductor structure, a method for forming a semiconductor structure, and a memory are provided. The method for forming the semiconductor structure in the disclosure includes: providing a base, the base including a substrate and an insulating dielectric layer, the substrate including a plurality of first trenches spaced apart from each other in a first direction, and the insulating dielectric layer being filled in each of the plurality of first trenches; patterning and etching the base to form a plurality of second trenches spaced apart from each other in a second direction, the second direction intersecting with the first direction; forming a word line structure in each of the plurality of second trenches; forming an air gap between each two adjacent word line structures of a plurality of word line structures; and sealing the air gap.

Abstract: Provided are a memory structure, a semiconductor structure and a method for manufacturing same. The semiconductor structure includes: a substrate, isolation structures provided in the substrate, delimiting an active area in the substrate, the active area including a channel region, and a source region and a drain region at opposite sides of the channel region; a gate structure, located on an upper surface of the substrate and covering the channel region; a source and a drain, located at opposite sides of the gate structure, respectively, the source in contact with the source region, the drain in contact with the drain region, and each of the source and the drain having a tooth-shaped portion; and a first contact plug and a second contact plug, located at the opposite sides of the gate structure, respectively, and connected to the tooth-shaped portion of the source and the tooth-shaped portion of the drain, respectively.

Abstract: Embodiments of the present disclosure relate to a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a substrate; etching the substrate to form a plurality of body structures arranged at intervals in a first direction, wherein a space between adjacent ones of the body structures is filled with a first isolation layer, each of the body structures includes a body layer and a plurality of body pillars that are discrete and are located on the body layer, the plurality of body pillars are arranged at intervals along a second direction, and the first direction is different from the second direction; etching a part of the body layer between adjacent ones of the body pillars, to form a plurality of openings in the body layer; and siliconizing the body layer through the plurality of openings.

Abstract: A method for manufacturing a memory includes: providing a substrate provided with bit lines, each bit line including a plurality of straight line segments connected end to end in sequence, and adjacent straight line segments have an included angle therebetween; forming active pillars and insulating layers on the substrate, each straight line segment of each bit line being electrically connected with at least two active pillars, each insulating layer extending in a first direction and covering the outer peripheral surface of the active pillar; filling a first support layer between adjacent insulating layers; removing part away from the substrate, of each insulating layer to form a filling space; and forming a dielectric layer and a conductive layer between parts exposed in the filling space and close to the substrate, of the active pillars.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which relate to the field of semiconductors. The method includes: providing a base; forming a plurality of first trenches extending along a first direction in the base, the first trenches forming the base into semiconductor layers arranged at intervals, and filling the first trenches with a first isolation layer; forming a plurality of second trenches extending along a second direction in the semiconductor layers and the first isolation layer, to form the semiconductor layers into a plurality of separate semiconductor pillars and initial bit lines located below the semiconductor pillars; forming third trenches parallel to the first trenches at positions lower than the second trenches; and filling the second trenches and the third trenches with a second isolation layer, where a part of the second isolation layer in the third trenches has gaps.

Abstract: The invention provides a sense amplifier circuit, a method for operating same, and a fabrication method for same. The sense amplifier circuit includes: an amplifier electrically connected to a memory cell of a semiconductor memory; and a pre-amplifier located between the amplifier and the memory cell, where the pre-amplifier is configured to pre-amplify an electrical signal transmitted from the memory cell to the amplifier. In this way, the pre-amplifier is provided between the amplifier and the memory cell, such that the electrical signal stored in the semiconductor memory can be output after two stages of amplification by the pre-amplifier and the amplifier, thereby avoiding the problem that the electrical signal output from the memory cell cannot be accurately received and output in a case of a small sense margin of a signal of the sense amplifier.

Abstract: Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure manufacturing method includes: providing a base substrate and an array region, the array region being composed of strip structures arranged in parallel, the base substrate being made of a same material as the array region, and a thickness of the base substrate being greater than a thickness of the array region; etching the strip structure to form discrete first strip structures; base substrate providing a second mask layer, an opening pattern of the second mask layer exposing the to-be-etched region and the side plane, and a right angle being formed between an orthographic projection of the side plane and the opening pattern; form a first active region, the first active region having a mapping right angle corresponding to the right angle.

Abstract: A method for manufacturing a semiconductor structure includes: a substrate; and a plurality of parallel word lines and a plurality of parallel bit lines on the substrate. For each bit line, the bit line is in a zigzag shape, each two adjacent segments among segments of the bit line with the zigzag shape form a first angle, the bit line has at least one first angle, and the bit line intersects the word lines to form a second angle.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base; bit lines, located on the base, and a material of the bit line including a metal semiconductor compound; semiconductor channels, each including a first doped region, a channel region and a second doped region arranged in sequence, and the first doped region being in contact with the bit line; a first dielectric layer, covering sidewall surfaces of the first doped regions, and a first interval being provided between parts of the first dielectric layer covering sidewalls of adjacent first doped regions on a same bit line; an insulating layer, covering sidewall surfaces of the channel regions; word lines, covering a sidewall surface of the insulating layer away from the channel regions, and a second interval being provided between adjacent word lines.

Abstract: The invention provides a semiconductor structure and a manufacturing method making the semiconductor structure. The method includes: providing a substrate; forming semiconductor pillars on the substrate; forming gate electrodes on the middle sidewalls of the semiconductor pillars; and performing dopant implantation to form source and drain regions. Since the gate-all-around (GAA) gates surrounding the semiconductor pillars are formed first, and the source region and the drain region are formed later by doping implantation, the precise position of the doping implantation can be ensured, thereby improving the fabrication accuracy of the semiconductor structure and improving the performance of the semiconductor structure.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The method for forming the semiconductor structure includes the following operations. A base is provided, in which the base includes a substrate, a first semiconductor layer and a second semiconductor layer sequentially formed on one another. A plurality of first isolation structures spaced apart from each other and a plurality of second isolation structures spaced apart from each other are formed in the base. A channel layer is formed in the first semiconductor layer, in which a through hole is provided between the channel layer and each of two first isolation structures adjacent to the channel layer. A gate structure is formed in the through hole.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a base; forming bit lines on the base, and forming semiconductor channels on surfaces of the bit lines away from the base, the semiconductor channel including a first doped region, a channel region and a second doped region arranged sequentially; forming a first dielectric layer, the first dielectric layer surrounding sidewalls of the semiconductor channels, and a first gap being provided between parts of the first dielectric layer located on sidewalls of adjacent semiconductor channels on a same bit line; forming a second dielectric layer, the second dielectric layer filling up the first gaps, and a material of the second dielectric layer being different from a material of the first dielectric layer; removing a part of the first dielectric layer to expose sidewalls of the channel regions.

Abstract: A test structure includes a plurality of word lines and a plurality of bit lines. A vertical gate-all-around (VGAA) transistor is formed at the intersection of each word line and each bit line. The test structure includes a first area and a second area. The second area is arranged outside the first area, the word lines in the first area and the word lines in the second area are disconnected, and the bit lines in the first area and the bit lines in the second area are disconnected. The plurality of VGAA transistors located in the first area form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested.

Abstract: Provided are a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a base; a bit line; and a semiconductor channel including a first doped region, a channel region, and a second doped region that are sequentially arranged, where the first doped region contacts the bit line, and the first doped region, the channel region, and the second doped region are doped with first-type doped ions. The channel region is further doped with second-type doped ions, enabling a concentration of majority carriers in the channel region to be less than a concentration of majority carriers in the first doped region and a concentration of majority carriers in the second doped region. The first-type doped ions are one of N-type ions or P-type ions, and the second-type doped ions are the other of N-type ions or P-type ions.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a base; forming a functional stack on the base, wherein the functional stack includes a first doped layer, a second doped layer and a third doped layer that are stacked sequentially, the first doped layer is provided on the base, dopant ions in the second doped layer are different from dopant ions in the first doped layer, and the dopant ions in the first doped layer are the same as dopant ions in the third doped layer; and removing a part of the functional stack to form a plurality of active pillars arranged at intervals.