Patents by Inventor Qinghua Zhong
Qinghua Zhong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8668805Abstract: A semiconductor device may be formed by the method comprising providing a patterned photoresist mask over the etch layer, the photoresist mask having at least one photoresist line having a pair of sidewalls ending at a line end, placing a coating over the at least one photoresist line comprising at least one cycle, wherein each cycle comprises: a) depositing a polymer layer over the photoresist line, wherein an amount of polymer at the line end is greater than an amount of polymer on the sidewalls, and b) hardening the polymer layer, and etching features into the etch layer through the photoresist mask, wherein a line end shortening (LES) is less than or equal to 1.Type: GrantFiled: June 30, 2008Date of Patent: March 11, 2014Assignee: Lam Research CorporationInventors: Gowri Kota, Frank Y. Lin, Qinghua Zhong
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Publication number: 20140051256Abstract: A method for etching a dielectric layer disposed below a patterned organic mask with features, with hardmasks at bottoms of some of the organic mask features is provided. An etch gas is provided. The etch gas is formed into a plasma. A bias RF with a frequency between 2 and 60 MHz is provided that provides pulsed bias with a pulse frequency between 10 Hz and 1 kHz wherein the pulsed bias selectively deposits on top of the organic mask with respect to the dielectric layer.Type: ApplicationFiled: August 15, 2012Publication date: February 20, 2014Applicant: LAM RESEARCH CORPORATIONInventors: Qinghua ZHONG, Siyi LI, Armen KIRAKOSIAN, Yifeng ZHOU, Ramkumar VINNAKOTA, Ming-Shu KUO, Srikanth RAGHAVAN, Yoshie KIMURA, Tae Won KIM, Gowri KAMARTHY
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Publication number: 20130267097Abstract: A method for forming features through a photoresist mask into an underlying layer is provided. The photoresist mask has patterned mask features. The photoresist mask has patterned mask features. A treatment gas containing H2 and N2 is provided. A plasma is generated from the treatment gas, and the photoresist mask is exposed to the plasma. The treatment gas is stopped, and then the features are etched into the underlying layer through the plasma-treated photoresist mask.Type: ApplicationFiled: April 5, 2012Publication date: October 10, 2013Applicant: LAM RESEARCH CORPORATIONInventors: Ratndeep SRIVASTAVA, Qinghua ZHONG, Tae Won KIM, Gowri KAMARTHY
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Patent number: 8431461Abstract: A method for forming devices with silicon gates over a substrate is provided. Silicon nitride spacers are formed on sides of the silicon gates. An ion implant is provided using the silicon nitride spacers as masks to form ion implant regions. A nonconformal layer is selectively deposited over the spacers and gates that selectively deposits a thicker layer on tops of the gates and spacers and between spacers than on sidewalls of the silicon nitride spacers. Sidewalls of the nonconformal layer are etched away on sidewalls of the silicon nitride spacers. The silicon nitride spacers are trimmed.Type: GrantFiled: December 16, 2011Date of Patent: April 30, 2013Assignee: Lam Research CorporationInventors: Qinghua Zhong, Yoshie Kimura, Tae Won Kim, Qian Fu, Gladys Lo, Ganesh Upadhyaya, Yoko Yamaguchi
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Patent number: 8298949Abstract: A method of forming spacers from a non-silicon oxide, silicon containing spacer layer with horizontal surfaces and sidewall surfaces over a substrate is provided. A plasma oxidation treatment is provided to form a silicon oxide coating over the spacer layer, wherein the silicon oxide coating provides a horizontal coating on the horizontal surfaces and sidewall coatings on the sidewall surfaces of the spacer layer. An anisotropic main etch that selectively etches horizontal surfaces of the spacer layer and silicon oxide coating with respect to sidewall surfaces of the spacer layer and the sidewall coatings of the silicon oxide coating is provided. The spacer layer is etched, wherein the sidewall coatings of the silicon oxide coating protect sidewall surfaces of the spacer layer.Type: GrantFiled: January 7, 2009Date of Patent: October 30, 2012Assignee: Lam Research CorporationInventors: Qinghua Zhong, Sung Cho, Gowri Kamarthy, Linda Braly
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Publication number: 20100173496Abstract: A method of forming spacers from a non-silicon oxide, silicon containing spacer layer with horizontal surfaces and sidewall surfaces over a substrate is provided. A plasma oxidation treatment is provided to form a silicon oxide coating over the spacer layer, wherein the silicon oxide coating provides a horizontal coating on the horizontal surfaces and sidewall coatings on the sidewall surfaces of the spacer layer. An anisotropic main etch that selectively etches horizontal surfaces of the spacer layer and silicon oxide coating with respect to sidewall surfaces of the spacer layer and the sidewall coatings of the silicon oxide coating is provided. The spacer layer is etched, wherein the sidewall coatings of the silicon oxide coating protect sidewall surfaces of the spacer layer.Type: ApplicationFiled: January 7, 2009Publication date: July 8, 2010Applicant: LAM RESEARCH CORPORATIONInventors: Qinghua Zhong, Sung Cho, Gowri Kamarthy, Linda Braly
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Patent number: 7491343Abstract: A method for etching features in an etch layer is provided. A patterned photoresist mask is provided over the etch layer, the photoresist mask having at least one photoresist line having a pair of sidewalls ending at a line end is provided. A polymer layer is placed over the at least one photoresist line, wherein a thickness of the polymer layer at the line end of the photoresist line is greater than a thickness of the polymer layer on the sidewalls of the photoresist line. Features are etched into the etch layer through the photoresist mask, wherein a line end shortening (LES) ratio is less than or equal to 1.Type: GrantFiled: January 10, 2007Date of Patent: February 17, 2009Assignee: Lam Research CorporationInventors: Yoko Yamaguchi Adams, Gowri Kota, Frank Y. Lin, Qinghua Zhong
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Publication number: 20080268211Abstract: A semiconductor device may be formed by the method comprising providing a patterned photoresist mask over the etch layer, the photoresist mask having at least one photoresist line having a pair of sidewalls ending at a line end, placing a coating over the at least one photoresist line comprising at least one cycle, wherein each cycle comprises: a) depositing a polymer layer over the photoresist line, wherein an amount of polymer at the line end is greater than an amount of polymer on the sidewalls, and b) hardening the polymer layer, and etching features into the etch layer through the photoresist mask, wherein a line end shortening (LES) is less than or equal to 1.Type: ApplicationFiled: June 30, 2008Publication date: October 30, 2008Applicant: LAM RESEARCH CORPORATIONInventors: Gowri KOTA, Frank Y. LIN, Qinghua ZHONG
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Patent number: 7407597Abstract: A method for etching features in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with at least one photoresist line having a pair of sidewalls ending at a line end. A coating is placed over the photoresist line comprising at least one cycle of depositing a polymer layer over the photoresist line, wherein an amount of polymer at the line end is greater than an amount of polymer on the sidewalls, and hardening the polymer layer. Features are etched into the etch layer through the photoresist mask, wherein a line end shortening (LES) is less than or equal to 1.Type: GrantFiled: September 14, 2006Date of Patent: August 5, 2008Assignee: LAM Research CorporationInventors: Gowri Kota, Frank Y. Lin, Qinghua Zhong
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Publication number: 20080087637Abstract: A method for etching features in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with at least one photoresist line having a pair of sidewalls ending at a line end. A coating is placed over the photoresist line comprising at least one cycle of depositing a polymer layer over the photoresist line, wherein an amount of polymer at the line end is greater than an amount of polymer on the sidewalls, and hardening the polymer layer. Features are etched into the etch layer through the photoresist mask, wherein a line end shortening (LES) is less than or equal to 1.Type: ApplicationFiled: September 14, 2006Publication date: April 17, 2008Applicant: LAM Research CorporationInventors: Gowri Kota, Frank Y. Lin, Qinghua Zhong
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Publication number: 20080087639Abstract: A method for etching features in an etch layer is provided. A patterned photoresist mask is provided over the etch layer, the photoresist mask having at least one photoresist line having a pair of sidewalls ending at a line end is provided. A polymer layer is placed over the at least one photoresist line, wherein a thickness of the polymer layer at the line end of the photoresist line is greater than a thickness of the polymer layer on the sidewalls of the photoresist line. Features are etched into the etch layer through the photoresist mask, wherein a line end shortening (LES) ratio is less than or equal to 1.Type: ApplicationFiled: January 10, 2007Publication date: April 17, 2008Inventors: Yoko Adams, Gowri Kota, Frank Lin, Qinghua Zhong
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Patent number: 6281093Abstract: A new method of fabricating shallow trench isolations has been achieved. A silicon dioxide layer is formed overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the silicon dioxide layer. The silicon nitride layer is patterned to expose the semiconductor substrate where shallow trench isolations are planned. Ions are implanted into the exposed semiconductor substrate. The implanting damages any passive surface materials overlying the semiconductor substrate. The exposed semiconductor substrate is etched down to form trenches. The damaged passive surface materials are removed during the etching down to thereby prevent trench cone formation. A trench filling layer is deposited to fill the trenches. The trench filling layer is polished down to complete the shallow trench isolations in the manufacture of the integrated circuit device.Type: GrantFiled: July 19, 2000Date of Patent: August 28, 2001Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Yelehanka Ramachandramurthy Pradeep, Qinghua Zhong, Zheng Zou, Henry Gerung
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Patent number: 6124927Abstract: A new method of controlling the level of cleaning of the etch chamber by measuring the light emission caused by particles within the plasma of the etch chamber. The etch chamber clean process is invoked as soon as the level of contaminants within the etch chamber is observed as being too high. This measuring of the contaminants within the etch chamber is performed by measuring the particle light emission. The etch chamber cleaning process is considered complete when the light intensity created by existing particles in the chamber drops by a certain percentage.Type: GrantFiled: May 19, 1999Date of Patent: September 26, 2000Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Qinghua Zhong, Zou Zheng, Yelehanka Ramachandra Murthy Pradeep, Zhou Mei Sheng
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Patent number: 6001706Abstract: A method was achieved for fabricating field oxide regions (shallow trench isolation) having raised portions which are self-aligned and extend over edges of device areas. This results in FETs with improved sub-threshold characteristics and lower sub-threshold leakage currents. The method consists of forming a pad oxide and depositing a doped polysilicon layer and a hard mask layer on a silicon substrate. Shallow trenches are etched through the hard mask, doped polysilicon layer and partially into the silicon substrate. A thermal oxidation is used to form a liner oxide in the trenches and to oxidize, at a higher oxidation rate, the sidewalls of the doped polysilicon layer to form an oxide over the edges of the device areas. A gap-fill oxide is deposited in the trenches and chemical mechanical polished (CMP) back to the polysilicon layer. The remaining polysilicon layer over the device areas is selectively removed to provide a field oxide having raised portions formed over the edges of the device areas.Type: GrantFiled: December 8, 1997Date of Patent: December 14, 1999Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Poh Suan Tan, Lap Chan, Qinghua Zhong, Qian Gang