Abstract: Devices, methods and techniques related to high voltage and high-power diamond transistors are disclosed. In one example aspect, a switch operable under high-voltage and high-power includes a P-type diamond layer doped with an acceptor material, a first N-type diamond layer doped with a donor material and in contact with one side of the P-type diamond layer, a light blocking layer comprising the one or more apertures configured to allow the light to enter the first N-type diamond layer, a source contact and a drain contact that are at least partially in contact with the P-type diamond layer, and the gate in contact with at least an area of the first N-type diamond layer that corresponds to one of the one or more apertures. The gate can be positioned on the backside of the substrate.

Abstract: An apparatus, in accordance with one embodiment, includes a superjunction device having a voltage sustaining layer formed of a semiconductor material and a dopant in the voltage sustaining layer. The dopant is for distributing an electric field within the voltage sustaining layer. The dopant is more concentrated along a sidewall of the voltage sustaining layer than toward a center of the voltage sustaining layer, the sidewall extending at least a portion of the distance between a top surface and a bottom surface of a voltage sustaining layer. Methods of electric field-enhanced dopant diffusion to form a superjunction device are also presented.

Abstract: In one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of three dimensional (3D) structures above the substrate, a gate region, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure. The gate region is present on a portion of an upper surface of the second region and the gate region is coupled to a portion of the at least one vertical sidewall of each 3D structure.

Abstract: According to one embodiment, a device includes a first electrode, a second electrode spaced from the first electrode, a well extending between the first electrode and the second electrode, one or more chalcogens in the well, and at least one halogen mixed with the one or more chalcogens in the well. In addition, the chalcogens are selected from the group consisting of sulfur, selenium, tellurium, and polonium.

Abstract: Devices, systems and methods for solid-state X-ray detection with high temporal resolution are described. An example method includes receiving an X-ray pulse in a semiconductor chip resulting in an electron cloud being formed in the semiconductor chip, applying a first set of voltages across a first plurality of drift cathode strips on a first side of the semiconductor chip and a second plurality of drift cathode strips on a second side of the semiconductor chip, applying a second set of voltages to across the first and the second plurality of drift cathode strips to form an electric field having a linear profile to cause the electron cloud to drift along the middle of the semiconductor chip, and activating a counter cathode on the second side and one or more readout anodes on the first side to collect the electron cloud after spreading in the middle section of the semiconductor chip.

Abstract: An apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a first semiconductor material, an array of three dimensional (3D) structures above the substrate, a sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, and an isolation region positioned between the 3D structures. Each 3D structure includes the first semiconductor material. The sidewall heterojunction layer includes a second semiconductor material, where the first and second semiconductor material have different bandgaps.

Abstract: According to one embodiment, a method includes performing a plasma etching process on a masked III-V semiconductor, and forming a passivation layer on etched portions of the III-V semiconductor. The passivation layer includes at least one of a group III element and/or a metal from the following: Ni, Cr, W, Mo, Pt, Pd, Mg, Ti, Zr, Hf, Y, Ta, and Sc.

Abstract: In one embodiment, a method of forming a vertical transistor includes forming a layer comprising a semiconductor material above a substrate, defining three dimensional (3D) structures in the layer, forming a second region in at least one vertical sidewall of each 3D structure, and forming an isolation region between the 3D structures. In another embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of 3D structures above the substrate, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure.

Abstract: In one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of three dimensional (3D) structures above the substrate, a gate region, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure. The gate region is present on a portion of an upper surface of the second region and the gate region is coupled to a portion of the at least one vertical sidewall of each 3D structure.

Abstract: According to one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a semiconductor material; an array of three dimensional (3D) structures above the substrate; and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, where the second region includes a portion of at least one vertical sidewall of the 3D structure.

Abstract: In one embodiment, a product includes a structure comprising a material of a Group-III-nitride having a dopant, where a concentration of the dopant in the structure has a concentration gradient characteristic of diffusion of the dopant inward from at least a portion of a surface of the structure in a direction substantially normal to the portion of the surface. The structure has less than 1% decomposition of the Group-III-nitride at the surface of the structure.

Abstract: According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.

Abstract: According to one embodiment, a product includes an array of three dimensional structures, where each of the three dimensional structure includes a semiconductor material; a cavity region between each of the three dimensional structures; and a first material in contact with at least one surface of each of the three dimensional structures, where the first material is configured to provide high energy particle and/or ray emissions.

Abstract: According to one embodiment, a product includes an array of three dimensional structures, a cavity region between each of the three dimensional structures, and a first material in contact with at least one surface of each of the three dimensional structures. In addition, each of the three dimensional structures includes a semiconductor material, where at least one dimension of each of the three dimensional structures is in a range of about 0.5 microns to about 10 microns. Moreover, the first material is configured to provide high energy particle and/or ray emissions.

Abstract: In one embodiment, a product includes a structure comprising a material of a Group-III-nitride having a dopant, where a concentration of the dopant in the structure has a concentration gradient characteristic of diffusion of the dopant inward from at least a portion of a surface of the structure in a direction substantially normal to the portion of the surface. The structure has less than 1% decomposition of the Group-III-nitride at the surface of the structure.

Abstract: According to one embodiment, a method includes performing a plasma etching process on a masked III-V semiconductor, and forming a passivation layer on etched portions of the III-V semiconductor. The passivation layer includes at least one of a group III element and/or a metal from the following: Ni, Cr, W, Mo, Pt, Pd, Mg, Ti, Zr, Hf, Y, Ta, and Sc.

Abstract: According to one embodiment, a device includes a first electrode, a second electrode spaced from the first electrode, a well extending between the first electrode and the second electrode, one or more chalcogens in the well, and at least one halogen mixed with the one or more chalcogens in the well. In addition, the chalcogens are selected from the group consisting of sulfur, selenium, tellurium, and polonium.

Abstract: According to one embodiment, a product includes an array of three dimensional structures, a cavity region between each of the three dimensional structures, and a first material in contact with at least one surface of each of the three dimensional structures. In addition, each of the three dimensional structures includes a semiconductor material, where at least one dimension of each of the three dimensional structures is in a range of about 0.5 microns to about 10 microns. Moreover, the first material is configured to provide high energy particle and/or ray emissions.

Abstract: In one embodiment, a method of forming a vertical transistor includes forming a layer comprising a semiconductor material above a substrate, defining three dimensional (3D) structures in the layer, forming a second region in at least one vertical sidewall of each 3D structure, and forming an isolation region between the 3D structures. In another embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of 3D structures above the substrate, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure.

Abstract: According to one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a semiconductor material; an array of three dimensional (3D) structures above the substrate; and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, where the second region includes a portion of at least one vertical sidewall of the 3D structure.