Abstract: Disclosed is a compound of formula I or a pharmaceutically acceptable salt, active metabolite, tautomer, stereoisomer, or prodrug thereof as BTK (Bruton's Tyrosine Kinase) inhibitors, which is useful for the treatment of autoimmune disease, inflammatory disease, cancer and potentially allergies.

Abstract: The present invention relates to a preparation method of an edible and biodegradable environmental-friendly tableware, and the present invention provides a preparation method of a natural macromolecule-based edible and degradable tableware, where the principles of endogenous diffusion and polymer crosslinking to prepare an edible tableware such as a straw, a cup and a bowl from a microscopic state. The tableware material of the present invention may degrade rapidly under natural conditions and requires no composting. The tableware prepared by the method of the present invention has an excellent water stability performance. In terms of material acquisition, carrageenan, sodium alginate and other raw materials are widely available and stable, and may constitute a good substitute for grain starch, wood, etc., and the material cost is low.

Abstract: A light emitting diode (LED) matrix driver includes a scan line switch coupled to a scan line of an LED matrix and adapted to be coupled to a signal ground; a first voltage clamp coupled to the scan line switch and the scan line; and a second voltage clamp coupled to the scan line.

Abstract: A light emitting diode (LED) matrix driver includes a scan line switch coupled to a scan line of an LED matrix and adapted to be coupled to a signal ground; a first voltage clamp coupled to the scan line switch and the scan line; and a second voltage clamp coupled to the scan line.

Abstract: A light-emitting diode (LED) display driver circuit includes: a set of channels, each channel of the set of channels having a respective current control circuit; and control circuitry coupled to each respective current control circuit and configured to adjust a respective control signal to each respective current control circuit responsive to an LED brightness estimate for each channel of the set of channels.

Abstract: A light-emitting diode (LED) display driver circuit includes: a set of channels, each channel of the set of channels having a respective current control circuit; and control circuitry coupled to each respective current control circuit and configured to adjust a respective control signal to each respective current control circuit responsive to an LED brightness estimate for each channel of the set of channels.

Abstract: In a described example, an apparatus includes: a first metal oxide semiconductor field effect transistor (MOSFET) coupled between a first input terminal for receiving a supply voltage and an output terminal for coupling to a load, and having a first gate terminal; an enable terminal coupled to the first gate terminal for receiving an enable signal; a first current mirror coupled between the first input terminal and a first terminal of a first series resistor and having an input coupled to the first gate terminal; and a second MOSFET coupled between the first gate terminal and the output terminal, and having a second gate terminal coupled to the first terminal of the first series resistor, the first series resistor having a second terminal coupled to the output terminal.

Abstract: A system for a network of one or more off-board subsystems is provided for controlling automobile subsystems such as vehicle lighting. Such a system may be compatible with a universal asynchronous receiver transmitter (UART) interface and it may address timing issues by using a protocol having a synchronization frame (sync frame) such that a clock signal may be recovered from the sync frame sent by an off-board master device 202, such as a microcontroller unit 208, to a satellite/slave 211 device. Such a protocol permits elimination of a crystal clock oscillator and phase-locked loop located at satellite, thereby dispensing with an otherwise significant cost.

Abstract: In a described example, an apparatus includes: a first metal oxide semiconductor field effect transistor (MOSFET) coupled between a first input terminal for receiving a supply voltage and an output terminal for coupling to a load, and having a first gate terminal; an enable terminal coupled to the first gate terminal for receiving an enable signal; a first current mirror coupled between the first input terminal and a first terminal of a first series resistor and having an input coupled to the first gate terminal; and a second MOSFET coupled between the first gate terminal and the output terminal, and having a second gate terminal coupled to the first terminal of the first series resistor, the first series resistor having a second terminal coupled to the output terminal.

Abstract: In a described example, an apparatus includes: a first metal oxide semiconductor field effect transistor (MOSFET) coupled between a first input terminal for receiving a supply voltage and an output terminal for coupling to a load, and having a first gate terminal; an enable terminal coupled to the first gate terminal for receiving an enable signal; a first current mirror coupled between the first input terminal and a first terminal of a first series resistor and having an input coupled to the first gate terminal; and a second MOSFET coupled between the first gate terminal and the output terminal, and having a second gate terminal coupled to the first terminal of the first series resistor, the first series resistor having a second terminal coupled to the output terminal.

Abstract: In a described example, an apparatus includes: a first metal oxide semiconductor field effect transistor (MOSFET) coupled between a first input terminal for receiving a supply voltage and an output terminal for coupling to a load, and having a first gate terminal; an enable terminal coupled to the first gate terminal for receiving an enable signal; a first current mirror coupled between the first input terminal and a first terminal of a first series resistor and having an input coupled to the first gate terminal; and a second MOSFET coupled between the first gate terminal and the output terminal, and having a second gate terminal coupled to the first terminal of the first series resistor, the first series resistor having a second terminal coupled to the output terminal.

Abstract: In a described example, an apparatus includes: a first metal oxide semiconductor field effect transistor (MOSFET) coupled between a first input terminal for receiving a supply voltage and an output terminal for coupling to a load, and having a first gate terminal; an enable terminal coupled to the first gate terminal for receiving an enable signal; a first current mirror coupled between the first input terminal and a first terminal of a first series resistor and having an input coupled to the first gate terminal; and a second MOSFET coupled between the first gate terminal and the output terminal, and having a second gate terminal coupled to the first terminal of the first series resistor, the first series resistor having a second terminal coupled to the output terminal.

Abstract: A system for a network of one or more off-board subsystems is provided for controlling automobile subsystems such as vehicle lighting. Such a system may be compatible with a universal asynchronous receiver transmitter (UART) interface and it may address timing issues by using a protocol having a synchronization frame (sync frame) such that a clock signal may be recovered from the sync frame sent by an off-board master device 202, such as a microcontroller unit 208, to a satellite/slave 211 device. Such a protocol permits elimination of a crystal clock oscillator and phase-locked loop located at satellite, thereby dispensing with an otherwise significant cost.

Abstract: In a described example, an apparatus includes: a first metal oxide semiconductor field effect transistor (MOSFET) coupled between a first input terminal for receiving a supply voltage and an output terminal for coupling to a load, and having a first gate terminal; an enable terminal coupled to the first gate terminal for receiving an enable signal; a first current mirror coupled between the first input terminal and a first terminal of a first series resistor and having an input coupled to the first gate terminal; and a second MOSFET coupled between the first gate terminal and the output terminal, and having a second gate terminal coupled to the first terminal of the first series resistor, the first series resistor having a second terminal coupled to the output terminal.

Abstract: A circuit comprises: a pass transistor; a first transistor comprising a gate coupled to the gate of the pass transistor, a source coupled to the source of the pass transistor, and a drain; a second transistor comprising a gate coupled to the gate of the pass transistor, a source coupled to the source of the pass transistor, and a drain; a first current mirror coupled to the drain of the first transistor; a second current mirror coupled to the drain of the second transistor, and coupled to the first current mirror; a feedback voltage circuit coupled to the drain of the pass transistor; an error amplifier comprising a first input port coupled to the feedback voltage circuit, and an output port coupled to the gate of the pass transistor; and a capacitor coupled to the second current mirror and to the first input port of the error amplifier.

Abstract: A circuit comprises: a pass transistor; a first transistor comprising a gate coupled to the gate of the pass transistor, a source coupled to the source of the pass transistor, and a drain; a second transistor comprising a gate coupled to the gate of the pass transistor, a source coupled to the source of the pass transistor, and a drain; a first current mirror coupled to the drain of the first transistor; a second current mirror coupled to the drain of the second transistor, and coupled to the first current mirror; a feedback voltage circuit coupled to the drain of the pass transistor; an error amplifier comprising a first input port coupled to the feedback voltage circuit, and an output port coupled to the gate of the pass transistor; and a capacitor coupled to the second current mirror and to the first input port of the error amplifier.

Abstract: A light emitting diode controller integrated circuit includes counter circuitry having inputs coupled to a clock signal input pin, a pulse width modulated signal input pin, and a sense input pin, and has a count output coupled to a gate drive signal output to an external power transistor. The power transistor is connected in series between a power lead, a sense resistor, and a light emitting diode. The sense input pin is coupled to the series connection between the resistor and the transistor. The counter circuitry provides a Ton_delay equal to a Toff_delay of the power transistor. By counting up during a Ton_delay and down during a Toff_delay, the controller can be used with power transistors of unknown characteristics.

Abstract: Methods, apparatus, systems and articles of manufacture for negative output voltage active clamping using a floating bandgap reference and temperature compensation are disclosed. An example load switch includes a floating bandgap reference circuit to generate a bandgap reference voltage. A resistor divider is to generate a resistor divider voltage. A temperature compensator to apply a temperature compensation current to the resistor divider to create a temperature compensated resistor divider voltage. A power transistor is to be enabled when the temperature compensated resistor divider voltage is less than the bandgap reference voltage. The example load switch can work under negative output voltage clamping and get better accuracy drain to source clamped voltage of power transistor for inductive load condition.

Abstract: A gate driver IC for driving an NMOS transistor having a drain coupled through a load to a power supply. A gate driver output drives the gate of the NMOS transistor. A comparator receives the drain voltage of the NMOS transistor and compares it to a reference voltage representative of a short circuit condition between the drain and the power supply. The comparator outputs a first value if the drain voltage is greater than the reference voltage and outputs a second value if the drain voltage is less than or equal to the reference voltage. Control circuitry receives the output of the first comparator and pulls the voltage of the gate driver output low if the comparator output is of the first value. Adaptive masking circuitry is operable, upon an application of an “on” signal to the gate driver output, to mask the output of the comparator such that a condition of the drain voltage being greater than the reference voltage does not cause the control circuitry to pull the voltage of the gate driver output low.

Abstract: A light emitting diode controller integrated circuit includes counter circuitry having inputs coupled to a clock signal input pin, a pulse width modulated signal input pin, and a sense input pin, and has a count output coupled to a gate drive signal output to an external power transistor. The power transistor is connected in series between a power lead, a sense resistor, and a light emitting diode. The sense input pin is coupled to the series connection between the resistor and the transistor. The counter circuitry provides a Ton_delay equal to a Toff_delay of the power transistor. By counting up during a Ton_delay and down during a Toff_delay, the controller can be used with power transistors of unknown characteristics.