Abstract: The present disclosure belongs to the technical field of integrated circuit packaging, and specifically relates to a through silicon via structure for three-dimensional integrated circuit packaging and a manufacturing method thereof.

Abstract: Disclosed is an SOI active interposer for three-dimensional packaging and a fabrication method thereof. An SOI substrate is used as the substrate, and a CMOS inverter is formed on the top silicon of the SOI by using standard integrated circuit manufacturing processes, so that short channel effect and latch-up effect can be suppressed. A via hole structure is etched on the SOI substrate between the PMOS and NMOS transistors of the CMOS inverter, which on the one hand can be used as a conductive channel between the chips in a vertical direction, and on the other hand, can be used as an electrical isolation layer between the PMOS and NMOS transistors.

Abstract: The invention pertains to the technical field of semiconductor devices, and specifically relates to a three-dimensional capacitor-inductor based on a high-functional-density through silicon via structure and a manufacturing method, The three-dimensional capacitor-inductor of the present invention includes: a substrate formed with a through silicon via; a three-dimensional capacitor, formed on a sidewall of the through silicon via, and sequentially including a first metal layer, a second insulating layer; and a second metal layer; and a three-dimensional inductor, composed of center-filled metal of the through silicon via and planar thick metal rewiring, wherein a first insulating layer is provided between the sidewall of the through silicon via and the three-dimensional capacitor, and a third insulating layer is provided between the three-dimensional capacitor and the three-dimensional inductor, The invention can effectively increase the values of capacitance and inductance in an integrated system, and at the

Abstract: Disclosed is a three-dimensional integrated system for DRAM chips and a fabrication method thereof. A plurality of trench structures are etched on the front and back of a silicon wafer; then, a TSV structure is etched between the two upper and lower trenches opposite to each other for electrical connection; then, DRAM chips are placed in the trenches, and copper-copper bonding is used to make the chips electrically connected to the TSV structure in a vertical direction; finally, redistribution is done to make the chips in a horizontal direction electrically connected. The invention can make full use of silicon materials, and can avoid problems such as warpage and deformation of an interposer. In addition, placing the chips in the trenches will not increase the overall package thickness, while protecting the chips from external impact.

Abstract: The invention pertains to the technical field of semiconductor devices, and specifically relates to a three-dimensional capacitor-inductor based on a high-functional-density through silicon via structure and a manufacturing method. The three-dimensional capacitor-inductor of the present invention includes: a substrate formed with a through silicon via; a three-dimensional capacitor, formed on a sidewall of the through silicon via, and sequentially including a first metal layer, a second insulating layer, and a second metal layer; and a three-dimensional inductor, composed of center-filled metal of the through silicon via and planar thick metal rewiring, wherein a first insulating layer is provided between the sidewall of the through silicon via and the three-dimensional capacitor, and a third insulating layer is provided between the three-dimensional capacitor and the three-dimensional inductor.

Abstract: Disclosed is a three-dimensional integrated system for DRAM chips and a fabrication method thereof. A plurality of trench structures are etched on the front and back of a silicon wafer; then, a TSV structure is etched between the two upper and lower trenches opposite to each other for electrical connection; then, DRAM chips are placed in the trenches, and copper-copper bonding is used to make the chips electrically connected to the TSV structure in a vertical direction; finally, redistribution is done to make the chips in a horizontal direction electrically connected. The invention can make full use of silicon materials, and can avoid problems such as warpage and deformation of an interposer. In addition, placing the chips in the trenches will not increase the overall package thickness, while protecting the chips from external impact.

Abstract: Disclosed is an SOI active interposer for three-dimensional packaging and a fabrication method thereof. An SOI substrate is used as the substrate, and a CMOS inverter is formed on the top silicon of the SOI by using standard integrated circuit manufacturing processes, so that short channel effect and latch-up effect can be suppressed. A via hole structure is etched on the SOI substrate between the PMOS and NMOS transistors of the CMOS inverter, which on the one hand can be used as a conductive channel between the chips in a vertical direction, and on the other hand, can be used as an electrical isolation layer between the PMOS and NMOS transistors.

Abstract: The present disclosure discloses a three-dimensional integration system of an RFID chip and a supercapacitor and a manufacturing method thereof.

Abstract: The present disclosure belongs to the technical field of integrated circuit packaging, and specifically relates to a through silicon via structure for three-dimensional integrated circuit packaging and a manufacturing method thereof.

Abstract: Embodiments of the specification disclose a risk address identification method and apparatus, and an electronic device. The risk address identification method includes: acquiring an address word sequence corresponding to an input address; determining an address word in the address word sequence, the determined address word matching a risk word corresponding to a risk address; generating an observation sequence corresponding to the address word sequence according to the determined address word; processing the observation sequence using a hidden Markov model obtained based on semantics learning before and after address words, to obtain a decision vector, wherein the decision vector represents probabilities of the risk address being matched by address words contained in the address word sequence; and identifying whether the input address is a risk address by making a classification decision on the decision vector.

Abstract: An input comprising a name to be matched is received, where the name includes a plurality of words. A first name set corresponding to the name is determined, where the first name set includes a plurality of elements. Each of the plurality of words is matched with each of the plurality of elements based on a similarity degree to generate a standard name set. Whether the name is synonymous with at least one standard name in the standard name set is determined, where one or more characters of the name is not identical with one or more characters of the standard name. In response to determining that the name is synonymous with the at least one standard name, a matching result of the name is generated.

Abstract: Embodiments of the specification disclose a risk address identification method and apparatus, and an electronic device. The risk address identification method includes: acquiring an address word sequence corresponding to an input address; determining an address word in the address word sequence, the determined address word matching a risk word corresponding to a risk address; generating an observation sequence corresponding to the address word sequence according to the determined address word; processing the observation sequence using a hidden Markov model obtained based on semantics learning before and after address words, to obtain a decision vector, wherein the decision vector represents probabilities of the risk address being matched by address words contained in the address word sequence; and identifying whether the input address is a risk address by making a classification decision on the decision vector.

Abstract: Embodiments of the specification disclose a risk address identification method and apparatus, and an electronic device. The risk address identification method includes: acquiring an address word sequence corresponding to an input address; determining an address word in the address word sequence, the determined address word matching a risk word corresponding to a risk address; generating an observation sequence corresponding to the address word sequence according to the determined address word; processing the observation sequence using a hidden Markov model obtained based on semantics learning before and after address words, to obtain a decision vector, wherein the decision vector represents probabilities of the risk address being matched by address words contained in the address word sequence; and identifying whether the input address is a risk address by making a classification decision on the decision vector.

Abstract: Embodiments of the specification disclose a risk address identification method and apparatus, and an electronic device. The risk address identification method includes: acquiring an address word sequence corresponding to an input address; determining an address word in the address word sequence, the determined address word matching a risk word corresponding to a risk address; generating an observation sequence corresponding to the address word sequence according to the determined address word; processing the observation sequence using a hidden Markov model obtained based on semantics learning before and after address words, to obtain a decision vector, wherein the decision vector represents probabilities of the risk address being matched by address words contained in the address word sequence; and identifying whether the input address is a risk address by making a classification decision on the decision vector.

Abstract: An input comprising a name to be matched is received, where the name includes a plurality of words. A first name set corresponding to the name is determined, where the first name set includes a plurality of elements. Each of the plurality of words is matched with each of the plurality of elements based on a similarity degree to generate a standard name set. Whether the name is synonymous with at least one standard name in the standard name set is determined, where one or more characters of the name is not identical with one or more characters of the standard name. In response to determining that the name is synonymous with the at least one standard name, a matching result of the name is generated.

Abstract: The disclosure, belonging to the technological field of semiconductor memory, specifically relates to a semi-floating-gate device which comprises at least a semiconductor substrate, a source region, a drain region, a floating gate, a control gate, a perpendicular channel region and a gated p-n junction diode used to connect the floating gate and the substrate. The semi-floating-gate device disclosed in the disclosure using the floating gate to store information and realizing charging or discharging of the floating gate through a gated p-n junction diode boasts small unit area, high chip density, low operating voltage in data storage and strong ability in data retain.

Abstract: The disclosure, belonging to the technological field of semiconductor memory, specifically relates to a semi-floating-gate device which comprises at least a semiconductor substrate, a source region, a drain region, a floating gate, a control gate, a perpendicular channel region and a gated p-n junction diode used to connect the floating gate and the substrate. The semi-floating-gate device disclosed in the disclosure using the floating gate to store information and realizing charging or discharging of the floating gate through a gated p-n junction diode boasts small unit area, high chip density, low operating voltage in data storage and strong ability in data retain.

Abstract: The disclosure, belonging to the technological field of semiconductor memory, specifically relates to a semi-floating-gate device which comprises at least a semiconductor substrate, a source region, a drain region, a floating gate, a control gate, a perpendicular channel region and a gated p-n junction diode used to connect the floating gate and the substrate. The semi-floating-gate device disclosed in the disclosure using the floating gate to store information and realizing charging or discharging of the floating gate through a gated p-n junction diode boasts small unit area, high chip density, low operating voltage in data storage and strong ability in data retain.

Abstract: The present invention belongs to the technical field of semiconductor memories, in particular to a metal oxide semiconductor (MOS) transistor structure integrated with a resistance random access memory (RRAM). The MOS transistor structure comprises a MOS transistor and a RRAM formed on a substrate, wherein a gate dielectric layer of said MOS transistor extends to the surface of a drain region of said MOS transistor; and the part of the gate dielectric layer on the surface of the drain region of said MOS transistor forms a resistance-variable storage layer of said RRAM. In this invention, the high-quality dielectric layer of the MOS transistor and the resistance-variable storage layer of the RRAM are obtained by primary atomic layer deposition which integrates the RRAM and MOS transistor together without increasing steps.

Abstract: The present invention discloses an inductive element formed by through silicon via interconnections. The inductive element formed by means of the special through silicon via interconnection by using through silicon via technology features advantages such as high inductance and density. Moreover, the through silicon via interconnection integrated process forming the inductive element is compatible with the ordinary through silicon interconnection integrated process without any other steps, thus making the process simple and steady. The inductive element using the present invention is applicable to the through silicon via package manufacturing of various chips, especially the package manufacturing of power control chips and radio-frequency chips.