Abstract: A method of rebooting a file system using a non-volatile memory is provided. The method comprising persistently storing critical information in the non-volatile memory, the critical information indicating a status of the file system; in response to a predetermined event, obtaining critical information of the file system stored in the non-volatile memory; determining if the file system has crashed based on the critical information; and rebooting from metadata in the non-volatile memory if it is determined that the file system has crashed.

Abstract: The present invention discloses polyetheretherketone/nano-hydroxyapatite (PEEK/NANO-HA) composites for selective laser sintering (SLS), and a preparation method thereof. The method for preparing the composites comprises steps of: selecting PEEK having a particle size of 10-100 ?m, and an aqueous solution of reaction precursor 1 and an aqueous solution of reaction precursor 2, uniformly dispersing the PEEK in the aqueous solution of reaction precursor 1, adding the aqueous solution of reaction precursor 2 dropwise in the mixed solution of the aqueous solution of reaction precursor 1 and the PEEK while stirring to adjust pH of the mixed solution to 10-12, and continuously reacting or 24-48 hours. The composites obtained by the preparation method of the present invention have the advantages of good biocompatibility, homogeneous morphology and good fluidity, and are advantageous to the powdering and shaping process during SLS.

Abstract: The present application relates to a computational active Solid-State Drive(SSD) storage device, comprising: an active interface configured for data communication with one or more host machines, the active interface being configured to at least receive one or more instructions from the one or more host machines; a CPU connected with the active interface; and non-volatile memory (NVM), wherein the NVM is configured to store metadata for utilisation by the CPU to handle the one or more instructions received from the one or more host machines.

Abstract: The present invention discloses polyetheretherketone/nano-hydroxyapatite (PEEK/NANO-HA) composites for selective laser sintering (SLS), and a preparation method thereof. The method for preparing the composites comprises steps of: selecting PEEK having a particle size of 10-100 ?m, and an aqueous solution of reaction precursor 1 and an aqueous solution of reaction precursor 2, uniformly dispersing the PEEK in the aqueous solution of reaction precursor 1, adding the aqueous solution of reaction precursor 2 dropwise in the mixed solution of the aqueous solution of reaction precursor 1 and the PEEK while stirring to adjust pH of the mixed solution to 10-12, and continuously reacting or 24-48 hours. The composites obtained by the preparation method of the present invention have the advantages of good biocompatibility, homogeneous morphology and good fluidity, and are advantageous to the powdering and shaping process during SLS.

Abstract: A method of maintaining data consistency in a tree, the method including the steps of: storing leaf nodes in non-volatile memory, the leaf nodes comprising actual data; storing internal nodes in a memory space where data consistency is not required; and miming a CPU instruction to maintain data consistency only during modification of the leaf nodes.

Abstract: A method of rebooting a file system using a non-volatile memory is provided. The method comprising persistently storing critical information in the non-volatile memory, the critical information indicating a status of the file system; in response to a predetermined event, obtaining critical information of the file system stored in the non-volatile memory; determining if the file system has crashed based on the critical information; and rebooting from metadata in the non-volatile memory if it is determined that the file system has crashed.

Abstract: A method of fabricating semiconductor device is provided. First, a recess having a substantially rectangular cross section is formed in a substrate. Then, oxide layers are formed on sidewalls and bottom of the recess by oxygen ion implantation process, wherein oxide layer on sidewalls of recess is thinner than oxide layer on bottom of recess. Thereafter, oxide layer on sidewalls of recess is completely removed, and only a portion of oxide layer on bottom of recess remains. Then, sidewalls of recess are shaped into ? form by orientation selective wet etching using oxide layer remained on bottom of recess as a stop layer. Finally, oxide layer on bottom of recess is removed. By forming oxide layer on bottom of recess and using it as stop layer in subsequent orientation selective wet etching, the disclosed method can prevent a ?-shaped recess with a cuspate bottom.

Abstract: A method is provided for fabricating MOS transistors. The method includes providing a semiconductor substrate having at least a first region and a second region; and forming first transistors on the semiconductor substrate. Wherein source/drain regions of the first transistors are configured as SiGe growth regions; and a first density of SiGe growth regions in the first region is smaller than a second density of SiGe growth regions in the second region. The method also includes forming dummy SiGe growth regions in the first region to increase the first density such that the total density of SiGe growth regions in the first region is in a range similar to the second density; and forming trenches in the first region and the second region and the dummy SiGe growth region. Further, the method includes forming embedded source/drain regions of the first transistors and dummy SiGe regions.

Abstract: A method for manufacturing a semiconductor device may include forming a gate structure that includes a dummy gate member on a substrate. The method may further include forming two first-type spacers such that the dummy gate member is positioned between the first-type spacers. The method may further include forming two second-type spacers such that the first-type spacers are positioned between the second-type spacers. The method may further include forming two third-type spacers such that the second-type spacers are positioned between the third-type spacers. The method may further include performing etch to remove the third-type spacers and to at least partially remove the second-type spacers. The method may further include removing at least a portion of the dummy gate member to form a space between remaining portions of the first-type spacers. The method may further include providing a metal material in the space for forming a metal gate member.

Abstract: A method for manufacturing a semiconductor device may include forming a gate structure that includes a dummy gate member on a substrate. The method may further include forming two first-type spacers such that the dummy gate member is positioned between the first-type spacers. The method may further include forming two second-type spacers such that the first-type spacers are positioned between the second-type spacers. The method may further include forming two third-type spacers such that the second-type spacers are positioned between the third-type spacers. The method may further include performing etch to remove the third-type spacers and to at least partially remove the second-type spacers. The method may further include removing at least a portion of the dummy gate member to form a space between remaining portions of the first-type spacers. The method may further include providing a metal material in the space for forming a metal gate member.

Abstract: A storage device is disclosed, in which the device comprises memory (222) divisible into multiple zones, each zone comprising a plurality of physical blocks of the memory (222) and for associating with a zone-based address map for mapping between logical and physical addresses of said zone. The multiple zones are configurable independently of each other, and the memory (222) is non-volatile or volatile memory. A related zone-based block management and address mapping method, and a zone-based block management and address map for a storage device are also disclosed.

Abstract: A method is provided for fabricating MOS transistors. The method includes providing a semiconductor substrate having at least a first region and a second region; and forming first transistors on the semiconductor substrate. Wherein source/drain regions of the first transistors are configured as SiGe growth regions; and a first density of SiGe growth regions in the first region is smaller than a second density of SiGe growth regions in the second region. The method also includes forming dummy SiGe growth regions in the first region to increase the first density such that the total density of SiGe growth regions in the first region is in a range similar to the second density; and forming trenches in the first region and the second region and the dummy SiGe growth region. Further, the method includes forming embedded source/drain regions of the first transistors and dummy SiGe regions.

Abstract: A buffer management apparatus (101) for managing transfer of data between a host processor (102) and a flash-based memory (114) is disclosed. The apparatus (101) comprises a buffer (110) having a memory for caching the data to be transferred, the memory being logically partitioned as a page-based buffer partition configured with a plurality of first memory pages, and a block-based buffer partition configured with a plurality of memory blocks. Each memory block includes the same number of memory pages as an erasable block in the flash-based memory, and the host processor (102) is configured to access the page-based buffer partition or the block-based buffer partition based on type of data to be transferred. A related method and a buffer for flash-based memory are also disclosed.

Abstract: A storage device is disclosed, in which the device comprises memory (222) divisible into multiple zones, each zone comprising a plurality of physical blocks of the memory (222) and for associating with a zone-based address map for mapping between logical and physical addresses of said zone. The multiple zones are configurable independently of each other, and the memory (222) is non-volatile or volatile memory. A related zone-based block management and address mapping method, and a zone-based block management and address map for a storage device are also disclosed.

Abstract: A method of fabricating semiconductor device includes forming a recess having a substantially rectangular section and forming an oxide layer on sidewalls and an oxide layer on a bottom of the recess by anisotropic oxidation, wherein the oxide layer on the sidewalls is thinner than the oxide layer on the bottom of recess. The method further includes completely removing the oxide layer on the sidewalls and partially removing the oxide layer on the bottom of the recess. The method also includes performing an orientation selective wet etching on the recess using a remaining oxide layer of the recess as a stop layer to shape the sidewalls into a ? shaped section. The method includes removing the remaining oxide layer using an isotropic wet etching.

Abstract: A method of fabricating semiconductor device includes forming a recess having a substantially rectangular section and forming an oxide layer on sidewalls and an oxide layer on a bottom of the recess by anisotropic oxidation, wherein the oxide layer on the sidewalls is thinner than the oxide layer on the bottom of recess. The method further includes completely removing the oxide layer on the sidewalls and partially removing the oxide layer on the bottom of the recess. The method also includes performing an orientation selective wet etching on the recess using a remaining oxide layer of the recess as a stop layer to shape the sidewalls into a ? shaped section. The method includes removing the remaining oxide layer using an isotropic wet etching.

Abstract: A method of fabricating semiconductor device is provided. First, a recess having a substantially rectangular cross section is formed in a substrate. Then, oxide layers are formed on sidewalls and bottom of the recess by oxygen ion implantation process, wherein oxide layer on sidewalls of recess is thinner than oxide layer on bottom of recess. Thereafter, oxide layer on sidewalls of recess is completely removed, and only a portion of oxide layer on bottom of recess remains. Then, sidewalls of recess are shaped into ? form by orientation selective wet etching using oxide layer remained on bottom of recess as a stop layer. Finally, oxide layer on bottom of recess is removed. By forming oxide layer on bottom of recess and using it as stop layer in subsequent orientation selective wet etching, the disclosed method can prevent a ?-shaped recess with a cuspate bottom.