Abstract: An image recognition neural network processing method includes: a compiler segments an image recognition neural network to obtain tiles of at least one network layer group; classifies the tiles of each network layer group; and for each network layer group, generates an assembly code and tile information of the network layer group according to a tile result and a classification result of the network layer group. The same type of tiles correspond to the same assembly function, each assembly code includes a code segment of the assembly function corresponding to each type of tiles, the tile information includes block information of each tile in the network layer group, the tile information used to instruct a neural network processor to, according to the block information therein, invoke a corresponding code segment to process image data of a corresponding tile when a target image is identified by the image recognition neural network.

Abstract: The present application provides a convolution calculation method, a convolution calculation apparatus, a terminal device, and a computer readable storage medium. The method includes: inputting an image to be processed into a deep learning model, and obtaining a to-be-blocked convolution group and a target size of a block from all convolution layers of the deep learning model; blocking all input channel data of a first to-be-blocked convolution layer in said convolution group according to the target size, a size of each block being the target size; obtaining an output result of said convolution group according to all blocks of all input channel data of said first convolution layer; inputting the output result of said convolution group to a specified network of the deep learning model. Sizes of blocks of the to-be-blocked convolution layer and bandwidth consumption can be adjusted to adapt to frequently updating and upgrading the deep learning model.

Abstract: An image analysis method and a related device are provided. The method includes: obtaining an input matrix of a network layer A, the input matrix of the network layer A obtained based on a target type image; obtaining a target convolution kernel and a target convolution step length corresponding to the network layer A, different network layers corresponding to different convolution step lengths; performing convolution calculation on the input matrix and the target convolution kernel according to the target convolution step length to obtain an output matrix of the network layer A, the output matrix used for representing a plurality of features included in the target type image; determining a target preset operation corresponding to the target type image according to a pre-stored mapping relationship between a type image and a preset operation; and performing the target preset operation according to the plurality of features comprised included in the target type image.

Abstract: A neural network processor and a control method are provided. The neural network processor includes a neural network processor cluster formed by multiple single-core neural network processors and a peripheral module. The peripheral module includes a main control unit and a DMA module. The DMA module is used to convey a first task descriptor to the main control unit. The main control unit is used to: analyze the first task descriptor, determine, according to an analysis result, a subtask to be distributed to each selected processor; modify the first task descriptor to acquire a second task descriptor respectively corresponding to each selected processor; and distribute each second task descriptor to each corresponding selected processor, and activate each selected processor to process the corresponding subtask. The main control unit schedules and manages all of the single-core neural network processors, thereby leveraging operational performance of the neural network processor.

Abstract: The present application provides a convolution calculation method, a convolution calculation apparatus, a terminal device, and a computer readable storage medium. The method includes: inputting an image to be processed into a deep learning model, and obtaining a to-be-blocked convolution group and a target size of a block from all convolution layers of the deep learning model; blocking all input channel data of a first to-be-blocked convolution layer in said convolution group according to the target size, a size of each block being the target size; obtaining an output result of said convolution group according to all blocks of all input channel data of said first convolution layer; inputting the output result of said convolution group to a specified network of the deep learning model. Sizes of blocks of the to-be-blocked convolution layer and bandwidth consumption can be adjusted to adapt to frequently updating and upgrading the deep learning model.

Abstract: An image recognition neural network processing method includes: a compiler segments an image recognition neural network to obtain tiles of at least one network layer group; classifies the tiles of each network layer group; and for each network layer group, generates an assembly code and tile information of the network layer group according to a tile result and a classification result of the network layer group. The same type of tiles correspond to the same assembly function, each assembly code includes a code segment of the assembly function corresponding to each type of tiles, the tile information includes block information of each tile in the network layer group, the tile information used to instruct a neural network processor to, according to the block information therein, invoke a corresponding code segment to process image data of a corresponding tile when a target image is identified by the image recognition neural network.

Abstract: An image analysis method and a related device are provided. The method includes: obtaining an input matrix of a network layer A, the input matrix of the network layer A obtained based on a target type image; obtaining a target convolution kernel and a target convolution step length corresponding to the network layer A, different network layers corresponding to different convolution step lengths; performing convolution calculation on the input matrix and the target convolution kernel according to the target convolution step length to obtain an output matrix of the network layer A, the output matrix used for representing a plurality of features included in the target type image; determining a target preset operation corresponding to the target type image according to a pre-stored mapping relationship between a type image and a preset operation; and performing the target preset operation according to the plurality of features included in the target type image.

Abstract: A neural network processor and a control method are provided. The neural network processor includes a neural network processor cluster formed by multiple single-core neural network processors and a peripheral module. The peripheral module includes a main control unit and a DMA module. The DMA module is used to convey a first task descriptor to the main control unit. The main control unit is used to: analyze the first task descriptor, determine, according to an analysis result, a subtask to be distributed to each selected processor; modify the first task descriptor to acquire a second task descriptor respectively corresponding to each selected processor; and distribute each second task descriptor to each corresponding selected processor, and activate each selected processor to process the corresponding subtask. The main control unit schedules and manages all of the single-core neural network processors, thereby leveraging operational performance of the neural network processor.

Abstract: A processor and a power supply ripple reduction method are provided. The processor is connected to a power supply and an external memory and includes a controller, a power control unit and a processing unit. The processing unit includes an input buffer, an arithmetic unit, and an output buffer. The controller is used to determine an initial waiting cycle number N1 and a waiting cycle decrement number N2 of the processing unit. The power supply control unit is used to transmit, when the processor starts operations, a first control signal to the processing unit according to N1 and N2. The processing unit reads, upon receiving the first control signal, data to be processed from the external memory (12), buffers the read data in the input buffer, transmits the buffered data from the input buffer to the arithmetic unit to perform computation, and saves a computation result into the output buffer.

Abstract: An algorithm program loading method and a related apparatus are provided. The method includes: determining basic storage capacity of a second storage resource; obtaining an algorithm program, determining whether the algorithm capacity of the algorithm program is greater than the basic storage capacity, and if the algorithm capacity of the algorithm program is greater than the basic storage capacity, segmenting the algorithm program by taking the basic storage capacity as a unit to obtain algorithm subprograms; controlling a direct memory access module to load a master control program of a neural network processor to a first storage resource and executing the master control program; and controlling the direct memory access module to load the first algorithm subprogram in the algorithm subprograms to the second storage resource, confirming that the loading of the first algorithm subprogram is completed, executing the first algorithm subprogram, and loading in parallel a second algorithm subprogram.

Abstract: An algorithm program loading method and a related apparatus are provided. The method includes: determining basic storage capacity of a second storage resource; obtaining an algorithm program, determining whether the algorithm capacity of the algorithm program is greater than the basic storage capacity, and if the algorithm capacity of the algorithm program is greater than the basic storage capacity, segmenting the algorithm program by taking the basic storage capacity as a unit to obtain algorithm subprograms; controlling a direct memory access module to load a master control program of a neural network processor to a first storage resource and executing the master control program; and controlling the direct memory access module to load the first algorithm subprogram in the algorithm subprograms to the second storage resource, confirming that the loading of the first algorithm subprogram is completed, executing the first algorithm subprogram, and loading in parallel a second algorithm subprogram.

Abstract: A data processing method includes: an electronic device concurrently sending N storage requests for Q times to a memory in each polling by a processor, wherein the N storage requests are used for requesting the memory to store N rows of output data generated by N processing elements having continuous identifications among M processing elements, and Q is determined according to the number M of the processing elements and the number N of the storage requests; and by means of the memory, the electronic device storing a P-th row of output data generated by each of the M processing elements in a P-th polling according to received Q×N storage requests received from the processor. The present method can solve the problem of lower data storage efficiency in existing neural network models, a plurality of pieces of data may be stored at the same time by triggering concurrent requests to improve storage efficiency.

Abstract: A data processing method comprises: if detecting that a number of image data to be transferred is greater than zero wherein the number of image data is a product of a number of input image data and a number of output image data, and a first available storage space of a FIFO memory is greater than or equal to a storage space occupied by an N number of input image data, transferring the N input image data in a first memory to the first FIFO memory; if detecting that a number of weight data to be transferred is greater than zero wherein the number of weight data is a product of the number of input image data and the number of output image data, and a second available storage space of a second FIFO memory is greater than or equal to a storage space occupied by an M number of weight data, transferring the M weight data in a second memory to the second FIFO memory; when the number of input image data cached in the first FIFO memory and the number of weight data cached in the second FIFO memory are greater than or e

Abstract: A data processing method includes: an electronic device concurrently sending N storage requests for Q times to a memory in each polling by a processor, wherein the N storage requests are used for requesting the memory to store N rows of output data generated by N processing elements having continuous identifications among M processing elements, and Q is determined according to the number M of the processing elements and the number N of the storage requests; and by means of the memory, the electronic device storing a P-th row of output data generated by each of the M processing elements in a P-th polling according to received Q×N storage requests received from the processor. The present method can solve the problem of lower data storage efficiency in existing neural network models, a plurality of pieces of data may be stored at the same time by triggering concurrent requests to improve storage efficiency.

Abstract: A neural network chip and a related product are provided. The neural network chip (103) includes: a memory (102), a data reading/writing circuit, a convolution calculation circuit, wherein the memory is used for storing a feature map; the data reading/writing circuit is used for reading the feature map from the memory and execute an expansion and zero-padding operation on the feature according to configuration information of the feature map, and sending to the convolution calculation circuit (S401); and the convolution calculation circuit is used for performing convolution calculation on the data obtained after the expansion and zero-padding operation to implement a de-convolution operation (S402). The technical solution has advantages of saving memory usage and bandwidth.

Abstract: A data processing method comprises: if detecting that number of image data to be transferred is greater than zero, and a first available storage space of a FIFO memory is greater than or equal to a storage space occupied by N input image data, transferring the N input image data in a first memory to the first FIFO memory; if detecting that number of weight data to be transferred is greater than zero, and a second available storage space of a second FIFO memory is greater than or equal to a storage space occupied by M weight data, transferring the M weight data in a second memory to the second FIFO memory; when number of the input image data cached in the first FIFO memory and number of the weight data cached in the second FIFO memory are greater than or equal to 1, performing convolution operation on input image data i read from the first FIFO memory and weight data w read from the second FIFO memory to obtain output image data corresponding to an output index of the weight data w.

Abstract: A neural network chip and a related product are provided. The neural network chip (103) includes: a memory (102), a data reading/writing circuit, a convolution calculation circuit, wherein the memory is used for storing a feature map; the data reading/writing circuit is used for reading the feature map from the memory and execute an expansion and zero-padding operation on the feature according to configuration information of the feature map, and sending to the convolution calculation circuit (S401); and the convolution calculation circuit is used for performing convolution calculation on the data obtained after the expansion and zero-padding operation to implement a de-convolution operation (S402). The technical solution has advantages of saving memory usage and bandwidth.

Abstract: Provided are a data transmission method for a neural network, and a related product. The method includes the following steps: acquiring a weight specification of weight data stored in a memory, comparing the weight specification with a specification of a write memory in terms of size and determining a comparison result; according to the comparison result, dividing the write memory into a first-in first-out write memory and a multiplexing write memory; according to the comparison result, determining data reading policies of the first-in first-out write memory and the multiplexing write memory; and according to the data reading policies, reading weights from the first-in first-out write memory and the multiplexing write memory and loading the weights to a calculation circuit. The technical solution provided by the present application has the advantages of low power consumption and short calculation time.

Abstract: A calculation method includes: receiving a calculation instruction of a parse neural network, obtaining a weight CO*CI*n*m corresponding to the calculation instruction according to the calculation instruction; determining a KERNEL SIZE of the weight, scanning the weight with the KERNEL SIZE as a basic granularity to obtain a weight identifier, storing KERNEL corresponding to a second feature value of the weight identifier, deleting KERNEL corresponding to a first feature value of the weight identifier; scanning all values of the weight identifier; if the value is equal to a second specific value, extracting KERNEL and input data corresponding to the value, performing computation of the input data and the KERNEL to obtain an initial result; if the value is equal to the first feature value, not reading KERNEL and input data corresponding to the value; performing computation of all the initial results to obtain a calculation result of the calculation instruction.