Abstract: Techniques for multiple master devices accessing one or more slave devices via a single data bus are disclosed. According to one aspect of the techniques, a bus controller coupled between the master devices and the slave device, wherein the bus controller is configured to receive bus signals from the master devices, select one of the bus signals from one of the master devices and forwards the selected bus signal to the slave device. After the slave device receives the bus signal from the one of the master devices, the slave device sends a bus response signal to the master devices over the bus controller, and the master device from which the bus signal is selected identifies and receives the bus response signal.

Abstract: Techniques for extending memory addressing with more accessing range are disclosed. According to one aspect of the techniques, an apparatus for extending addressing space comprises a plurality of extended memories, each being allocated an unique identifier, a direct addressing memory reserving a data cell as a public identifier cell for receiving the identifier of each of the extended memories to be accessed, a decision unit determining that which one of the extended memories is to be accessed by comparing an identifier received by the public identifier cell with the identifier of each of the extended memories, and a mapping unit mapping one of the extended memories determined by the decision unit to be accessed onto the direct addressing memory so that the one of the extended memories can be indirectly accessed by directly accessing the direct addressing memory.

Abstract: Techniques for extending memory addressing with more accessing range are disclosed. According to one aspect of the techniques, an apparatus for extending addressing space comprises a plurality of extended memories, each being allocated an unique identifier, a direct addressing memory reserving a data cell as a public identifier cell for receiving the identifier of each of the extended memories to be accessed, a decision unit determining that which one of the extended memories is to be accessed by comparing an identifier received by the public identifier cell with the identifier of each of the extended memories, and a mapping unit mapping one of the extended memories determined by the decision unit to be accessed onto the direct addressing memory so that the one of the extended memories can be indirectly accessed by directly accessing the direct addressing memory.

Abstract: Techniques for multiple master devices accessing one or more slave devices via a single data bus are disclosed. According to one aspect of the techniques, a bus controller coupled between the master devices and the slave device, wherein the bus controller is configured to receive bus signals from the master devices, select one of the bus signals from one of the master devices and forwards the selected bus signal to the slave device. After the slave device receives the bus signal from the one of the master devices, the slave device sends a bus response signal to the master devices over the bus controller, and the master device from which the bus signal is selected identifies and receives the bus response signal.