Abstract: The present disclosure provides an inductive magnetic sensor, which includes a signal pre-amplifying measurement circuit, a feedback loop, a magnetic core and coil group, a low-noise autozero processing circuit, and an output protection module. The magnetic core and coil group is electrically connected between the signal pre-amplifying measurement circuit and the feedback loop, the signal pre-amplifying measurement circuit comprises the low-noise autozero processing circuit, and the feedback loop and the low-noise autozero processing circuit are electrically connected to the output protection module respectively. By introducing the resonant notch filter, it may extend the passband to the low frequency, and extend the low-frequency characteristic of the magnetic sensor, to obtain a better low-frequency magnetic sensor. The present disclosure further provides an electromagnetic prospecting equipment.

Abstract: Embodiments of process flows and methods are provided for forming a resistive switching random access memory (ReRAM). More specifically, process flows and methods are provided for reducing the forming voltage needed to form a conductive path in the ReRAM cells. A wide variety of plasma doping processes are used to introduce a plurality of different dopants into a metal-oxide dielectric film. By utilizing at least two different dopants, the plasma doping processes described herein reduce the forming voltage of the subsequently formed ReRAM cell compared to conventional processes that use only one dopant. In some embodiments, the forming voltage may be further reduced by applying a bias power during the plasma doping process, wherein the bias power is preselected to increase the number of ions introduced into the metal-oxide dielectric film during the plasma doping process.

Abstract: A resistive memory device with an embedded shoulder pulled sidewall spacer and method of forming. The method includes providing a patterned film stack containing a lower electrode layer, a dielectric filament layer on the lower electrode layer, and an upper electrode layer on the dielectric filament layer, depositing a conformal cap layer on the patterned film stack, dry etching the conformal cap layer to form a sidewall spacer on sidewalls of the patterned film stack, where a top of the sidewall spacer is recessed to below a top of the upper electrode layer by the dry etching. The method further includes encapsulating the patterned film stack in an isolation layer, and etching the isolation layer to expose the upper electrode layer without exposing the sidewall spacer.

Abstract: The invention relates to the field of pharmaceutical chemistry, and it particularly relates to a left-handed bicyclic morpholine and a pharmaceutically acceptable salt thereof, a preparation method therefor, a pharmaceutical composition and use thereof in the preparation of medicaments for preventing and/or treating liver diseases and the like.

Abstract: Embodiments of process flows and methods are provided for forming a resistive switching random access memory (ReRAM). More specifically, process flows and methods are provided for reducing the forming voltage needed to form a conductive path in the ReRAM cells. A wide variety of plasma doping processes are used to introduce a plurality of different dopants into a metal-oxide dielectric film. By utilizing at least two different dopants, the plasma doping processes described herein reduce the forming voltage of the subsequently formed ReRAM cell compared to conventional processes that use only one dopant. In some embodiments, the forming voltage may be further reduced by applying a bias power during the plasma doping process, wherein the bias power is preselected to increase the number of ions introduced into the metal-oxide dielectric film during the plasma doping process.

Abstract: A resistive random access memory (RERAM) apparatus and method for forming the apparatus are provided. Oxygen content control in the RERAM is provided. To provide oxygen content control, a via to an electrode of the RERAM is formed utilizing an oxygen-free plasma etch step. In one embodiment, the dielectric within which the via is formed is silicon nitride (SiN). In exemplary embodiments, the plasma chemistry is a hydrofluorocarbon (CxHyFz)-based plasma chemistry or a fluorocarbon (CxFy)-based plasma chemistry. In one embodiment, the resistive layer of the RERAM is a metal oxide. In another embodiment, the oxygen concentrations in the electrode of the RERAM under the via and outside the via are the same after formation of the via.

Abstract: A method of plasma processing that includes maintaining a plasma processing chamber between 10° C. to 200° C., flowing oxygen and nitrogen into the plasma processing chamber, where a ratio of a flow rate of the nitrogen to a flow rate of oxygen is between about 1:5 and about 1:1, and etching a ruthenium/osmium layer by sustaining a plasma in the plasma processing chamber.

Abstract: A resistive random access memory (RERAM) apparatus and method for forming the apparatus are provided. Oxygen content control in the RERAM is provided. To provide oxygen content control, a via to an electrode of the RERAM is formed utilizing an oxygen-free plasma etch step. In one embodiment, the dielectric within which the via is formed is silicon nitride (SiN). In exemplary embodiments, the plasma chemistry is a hydrofluorocarbon (CxHyFz)-based plasma chemistry or a fluorocarbon (CxFy)-based plasma chemistry. In one embodiment, the resistive layer of the RERAM is a metal oxide. In another embodiment, the oxygen concentrations in the electrode of the RERAM under the via and outside the via are the same after formation of the via.

Abstract: A process and device is disclosed for etching a magnetroresistive random access memory device which includes at least one magnetic tunnel junction stack structure which includes an insulating layer disposed between first and second magnetic layers. The process includes the step of contacting a substrate with a chlorine containing plasma at a temperature no greater than 30 degrees Centigrade under conditions effective to convert at least a portion of the first and second magnetic layers and the insulating layer into metal chlorides. Next, the resulting product of the contacting step is treated with an organic solvent under conditions effective to remove the metal chlorides. The treatment can include rinsing away the metal chlorides either by dissolving the metal chlorides, or by reacting the metal chlorides with a reactive organic solvent, or both.

Abstract: A process and device is disclosed for etching a magnetroresistive random access memory device which includes at least one magnetic tunnel junction stack structure which includes an insulating layer disposed between first and second magnetic layers. The process includes the step of contacting a substrate with a chlorine containing plasma at a temperature no greater than 30 degrees Centigrade under conditions effective to convert at least a portion of the first and second magnetic layers and the insulating layer into metal chlorides. Next, the resulting product of the contacting step is treated with an organic solvent under conditions effective to remove the metal chlorides. The treatment can include rinsing away the metal chlorides either by dissolving the metal chlorides, or by reacting the metal chlorides with a reactive organic solvent, or both.

Abstract: Inclusion complexes of pinocembrin with cyclodextrin or its derivatives and their preparation are provided. The inclusion complexes can be used to make drugs.

Abstract: A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent the sidewalls of the at least one fin. A first epitaxial region is formed that covers both one of the recessed regions and a second portion of the at least one fin, such that the second portion extends outwardly from one of the gate spacers. A first epitaxial layer is formed within the one of the recessed regions by etching the first epitaxial region and the second portion of the at least one fin. A second epitaxial region is formed at a location adjacent one of the spacers and over the first epitaxial layer within one of the recessed regions.

Abstract: A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent the sidewalls of the at least one fin. A first epitaxial region is formed that covers both one of the recessed regions and a second portion of the at least one fin, such that the second portion extends outwardly from one of the gate spacers. A first epitaxial layer is formed within the one of the recessed regions by etching the first epitaxial region and the second portion of the at least one fin. A second epitaxial region is formed at a location adjacent one of the spacers and over the first epitaxial layer within one of the recessed regions.

Abstract: A semiconductor structure, and method of forming a semiconductor structure, that includes a gate structure on a semiconductor substrate, in which the gate structure includes a gate conductor and a high-k gate dielectric layer. The high-k gate dielectric layer is in contact with the base of the gate conductor and is present on the sidewalls of the gate conductor for a dimension that is less than ¼ the gate structure's height. The semiconductor structure also includes source regions and drain regions present in the semiconductor substrate on opposing sides of the gate structure.

Abstract: Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine-and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.

Abstract: The present invention relates to a method for resolution of a mixture of pinocembrin optical isomers, in particular a pinocembrin racemate, using a chiral primary amine or a chiral sulfinamide. The present invention also relates to a (R)-(+)-pinocembrin obtained by the method.

Abstract: A semiconductor structure, and method of forming a semiconductor structure, that includes a gate structure on a semiconductor substrate, in which the gate structure includes a gate conductor and a high-k gate dielectric layer. The high-k gate dielectric layer is in contact with the base of the gate conductor and is present on the sidewalls of the gate conductor for a dimension that is less than ¼ the gate structure's height. The semiconductor structure also includes source regions and drain regions present in the semiconductor substrate on opposing sides of the gate structure.

Abstract: Inclusion complexes of pinocembrin with cyclodextrin or its derivatives and their preparation are provided. The inclusion complexes can be used to make drugs.

Abstract: Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.

Abstract: Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.