Patents by Inventor Qingzhu ZHANG

Qingzhu ZHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220410252
    Abstract: The disclosure discloses a method of producing a magnesium alloy wheel hub, comprises the following steps: step 1, heating a magnesium alloy bar to 350-430° C. and keeping the temperature for 20 minutes; step 2, initially forging and forming the bar under a forging press, the forging speed is 6-15 mm/s; step 3, finally forging and forming the bar under a forging press, and the forging speed is 5-8 mm/s; step 4, testing the microstructure and material properties of the final forged blank to obtain the layered material property distribution on the thickness of the blank; step 5, according to the layered material property distribution on the thickness of the blank obtained in step 4, selecting the part that meets the requirements to make a magnesium alloy wheel hub.
    Type: Application
    Filed: January 14, 2022
    Publication date: December 29, 2022
    Inventors: Lixin Huang, Zuo Xu, Decai Kong, Jingru Shen, Meng Li, Tieqiang Chen, Qingzhu Zhang
  • Patent number: 11476328
    Abstract: A stacked nanowire or nanosheet gate-all-around device, including: a silicon substrate; stacked nanowires or nanosheets located on the silicon substrate, extending along a first direction gate stacks and including multiple nanowires or nanosheets that are stacked; a gate stack, surrounding each of the stacked nanowires or nanosheets, and extending along a second direction, where first spacers are located on two sidewalls of the gate stack in the first direction; source-or-drain regions, located at two sides of the gate stack along the first direction; a channel region, including a portion of the stacked nanowires or nanosheets that is located between the first spacers. A notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, and includes an isolator that isolates the stacked nanowires or nanosheets from the silicon substrate. A method for manufacturing the stacked nanowire or nanosheet gate-all-around device is further provided.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: October 18, 2022
    Inventors: Yongliang Li, Xiaohong Cheng, Qingzhu Zhang, Huaxiang Yin, Wenwu Wang
  • Publication number: 20220307118
    Abstract: The disclosure discloses a method for manufacturing special purpose vehicle wheels by using 7000 series aluminum alloys, comprising the following steps: step 1, smelting 7000 series aluminum alloys in a smelting furnace; step 2, making the solution obtained in step 1 into an aluminum alloy ingot blank through a spraying and forming process; step 3, extruding the aluminum alloy ingot blank of step 2 to obtain an extrusion bar; step 4, sawing the extrusion bar into blanks and heating them; step 5, rolling the blank into a cake; step 6, putting the cake into a press for forging and forming; step 7, spinning and forming the wheel rim. The wheel manufactured by the method for manufacturing special vehicle wheels with 7000 series aluminum alloys in the present disclosure has high and stable conductivity, qualified impact test and good bending and radial fatigue performance.
    Type: Application
    Filed: January 14, 2022
    Publication date: September 29, 2022
    Inventors: Tieqiang Chen, Zuo Xu, Zhihua Zhu, Qingzhu Zhang, Lixin Huang, Meng Li
  • Publication number: 20220310865
    Abstract: The invention discloses a laminated cell structure, the laminated cell structure comprising a top cell unit, a bottom cell unit, and an intermediate layer located between the top cell unit and the bottom cell unit; the intermediate layer being configured as a tunnel junction composed of a p+/n+ double-layer silicon thin film; the top cell unit comprising an electron transport layer, a perovskite photosensitive layer, a hole transport layer sequentially laminated in the direction from the distance to the vicinity with respect to the intermediate layer, and a front electrode provided on the electron transport layer; and the bottom cell unit being a PERC solar cell. The invention also correspondingly discloses a preparation method for the laminated cell structure. According to the invention, good perovskite cell performance can be obtained by adopting a silicon thin film tunnel junction structure. The laminated cell with the structure has high photoelectric conversion efficiency.
    Type: Application
    Filed: April 23, 2021
    Publication date: September 29, 2022
    Applicant: SUZHOU TALESUN SOLAR TECHNOLOGIES CO., LTD.
    Inventors: Shude ZHANG, Baoxing ZHAO, Zhichun NI, Qingzhu WEI, Weifei LIAN, Xin FU
  • Patent number: 11411091
    Abstract: A method for manufacturing a stacked gate-all-around nano-sheet CMOS device, including: providing a substrate with a fin structure, where a channel layer for an NMOS is a sacrificial layer for a PMOS, a channel layer for the PMOS is a sacrificial layer for the NMOS; and mobility of holes in the second material is greater than mobility of holes in the first material; forming a dummy gate stack extending across the fin structure; forming source-or-drain regions in the fin structure at two sides of the dummy gate stack; removing the dummy gate stack and the sacrificial layers covered by the dummy gate stack, to expose a surface of a part of the channel layer that is located between the source-or-drain regions, where a nano-sheet array is formed by the channel layer with the exposed surface; and forming a gate stack structure surrounding each nano sheet in the nano-sheet array.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 9, 2022
    Inventors: Huaxiang Yin, Tianchun Ye, Qingzhu Zhang, Jiaxin Yao
  • Publication number: 20220221905
    Abstract: The present application discloses an electronic device including a housing, support plates and a display panel. The housing is recessed inward to form one or more clearances penetrating the housing along a first direction. A number of the support plates is at least two, and one clearance is correspondingly arranged below adjoining parts of two adjacent support plates. The support plates are configured to support the display panel. The display panel is switchable between a folded position and an unfolded position. When the display panel is in the unfolded position, first surfaces of the support plates that abut against the display panel are flush.
    Type: Application
    Filed: January 14, 2021
    Publication date: July 14, 2022
    Inventors: Zhenhua LUO, Hao WU, Na AN, Xiao MA, Gang CI, Xinfeng GONG, Shaopeng XU, Zheng ZHANG, Qingzhu GUAN, Guochun WANG, Zuoxin YU, Dianzhong LIU, Zheng ZONG, Pengcheng DONG, Quan LONG, Qidong SUN
  • Patent number: 11387426
    Abstract: A flexible display panel and a flexible display device are provided. The flexible display panel includes a flexible screen layer and an elastic support layer; the flexible screen layer and the elastic support layer are stacked; the elastic support layer includes a support mechanism and an elastic mechanism, the support mechanism is configured to support the flexible screen layer and is rollable, and the elastic mechanism is configured to generate an anti-rolling elastic force to maintain flatness of the flexible screen layer if the flexible screen layer is unrolled.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: July 12, 2022
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shaopeng Xu, Hao Wu, Xuzhong Liu, Na An, Zongwei Luo, Baolei Guo, Gang Ci, Xiao Ma, Xinfeng Gong, Bin Xu, Zhenhua Luo, Zheng Zhang, Qingzhu Guan, Wei Su, Jinzhao Zhou, Guochun Wang, Zuoxin Yu, Dianzhong Liu
  • Publication number: 20220115513
    Abstract: A method for manufacturing a stacked gate-all-around nano-sheet CMOS device, including: providing a substrate with a fin structure, where a channel layer for an NMOS is a sacrificial layer for a PMOS, a channel layer for the PMOS is a sacrificial layer for the NMOS; and mobility of holes in the second material is greater than mobility of holes in the first material; forming a dummy gate stack extending across the fin structure; forming source-or-drain regions in the fin structure at two sides of the dummy gate stack; removing the dummy gate stack and the sacrificial layers covered by the dummy gate stack, to expose a surface of a part of the channel layer that is located between the source-or-drain regions, where a nano-sheet array is formed by the channel layer with the exposed surface; and forming a gate stack structure surrounding each nano sheet in the nano-sheet array.
    Type: Application
    Filed: October 30, 2019
    Publication date: April 14, 2022
    Inventors: Huaxiang YIN, Tianchun YE, Qingzhu ZHANG, Jiaxin YAO
  • Patent number: 11257933
    Abstract: A method for manufacturing a semiconductor device is provided. A first substrate and at least one second substrate are provided. A single crystal lamination structure is formed on the first substrate. The single crystal lamination structure includes at least one hetero-material layer and at least one channel material layer that are alternately laminated, each of the at least one hetero-material layer is bonded to an adjacent one of the at least one channel material layer at a side away from the first substrate, and each of the at least one channel material layer is formed from one of the at least one second substrate. At least one layer of nanowire or nanosheet is formed from the single crystal lamination structure. A gate dielectric layer and a gate which surround each of the at least one layer of nanowire or nanosheet is formed. A semiconductor device is also provided.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: February 22, 2022
    Assignee: Institute of Microelectronics, Chinese Academy
    Inventors: Huaxiang Yin, Qingzhu Zhang, Renren Xu
  • Patent number: 11069808
    Abstract: A negative capacitance field effect transistor (NCFET) and a manufacturing method thereof. The NCFET includes: a substrate structure, including a MOS region; a gate insulating dielectric structure, covering the MOS region; and a metal gate stack layer, covering the gate insulating dielectric structure. The gate insulating dielectric structure includes an interface oxide layer, a HfO2 layer, a doping material layer, and a ferroelectric material layer, which are sequentially stacked along a direction away from the substrate structure. A ferroelectric material in the ferroelectric material layer is HfxA1-xO2, A represents a doping element, and 0.1?x?0.9. A material forming the doping material layer is AyOz or A, and a ratio of y/z is equal to 1/2, 2/3, 2/5 or 1/1. Ferroelectric characteristics, material stability, and material reliability of the NCFET are improved by increasing domain polarity of the ferroelectric material.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 20, 2021
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Qingzhu Zhang, Zhaohao Zhang, Tianchun Ye
  • Publication number: 20210193822
    Abstract: A method for manufacturing a semiconductor device is provided. A first substrate and at least one second substrate are provided. A single crystal lamination structure is fonned on the first substrate. The single crystal lamination structure includes at least one hetero-material layer and at least one channel material layer that are alternately laminated, each of the at least one hetero-material layer is bonded to an adjacent one of the at least one channel material layer at a side away from the first substrate, and each of the at least one channel material layer is formed from one of the at least one second substrate. At least one layer of nanowire or nanosheet is formed from the single crystal lamination structure. A gate dielectric layer and a gate which surround each of the at least one layer of nanowire or nanosheet is formed. A semiconductor device is also provided.
    Type: Application
    Filed: September 23, 2020
    Publication date: June 24, 2021
    Inventors: Huaxiang YIN, Qingzhu ZHANG, Renren XU
  • Patent number: 11024708
    Abstract: A semiconductor device, including: a silicon substrate; multiple fin structures, formed on the silicon substrate, where each extends along a first direction; a shallow trench insulator, located among the multiple fin structures; a gate stack, intersecting with the multiple fin structures and extending along a second direction, where first spacers are formed on two sidewalls in the first direction of the gate stack; source-or-drain regions, formed on the multiple fin structures, and located at two sides of the gate stack along the first direction; and a channel region, including a portion of the multiple fin structures located between the first spacers. and notch structures. A notch structure recessed inward is located between each of the multiple fin structures and the silicon substrate. The notch structure includes an isolator that isolates each of the multiple fin structures from the silicon substrate.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: June 1, 2021
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Yongliang Li, Xiaohong Cheng, Qingzhu Zhang, Huaxiang Yin, Wenwu Wang
  • Publication number: 20210151561
    Abstract: A stacked nanowire or nanosheet gate-all-around device, including: a silicon substrate; stacked nanowires or nanosheets located on the silicon substrate, extending along a first direction gate stacks and including multiple nanowires or nanosheets that are stacked; a gate stack, surrounding each of the stacked nanowires or nanosheets, and extending along a second direction, where first spacers are located on two sidewalls of the gate stack in the first direction; source-or-drain regions, located at two sides of the gate stack along the first direction; a channel region, including a portion of the stacked nanowires or nanosheets that is located between the first spacers. A notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, and includes an isolator that isolates the stacked nanowires or nanosheets from the silicon substrate. A method for manufacturing the stacked nanowire or nanosheet gate-all-around device is further provided.
    Type: Application
    Filed: March 20, 2020
    Publication date: May 20, 2021
    Inventors: Yongliang LI, Xiaohong CHENG, Qingzhu ZHANG, Huaxiang YIN, Wenwu WANG
  • Publication number: 20210151557
    Abstract: A semiconductor device, including: a silicon substrate; multiple fin structures, formed on the silicon substrate, where each extends along a first direction; a shallow trench insulator, located among the multiple fin structures; a gate stack, intersecting with the multiple fin structures and extending along a second direction, where first spacers are formed on two sidewalls in the first direction of the gate stack; source-or-drain regions, formed on the multiple fin structures, and located at two sides of the gate stack along the first direction; and a channel region, including a portion of the multiple fin structures located between the first spacers. and notch structures. A notch structure recessed inward is located between each of the multiple fin structures and the silicon substrate. The notch structure includes an isolator that isolates each of the multiple fin structures from the silicon substrate.
    Type: Application
    Filed: March 20, 2020
    Publication date: May 20, 2021
    Inventors: Yongliang LI, Xiaohong CHENG, Qingzhu ZHANG, Huaxiang YIN, Wenwu WANG
  • Publication number: 20200335596
    Abstract: A gate-all-around nanowire device and a method for forming the gate-all-around nanowire device. A first fin and a dielectric layer on the first fin are formed on a substrate. The first fin includes the at least one first epitaxial layer and the at least one second epitaxial layer that are alternately stacked. The dielectric layer exposes a channel region of the first fin. A doping concentration at a lateral surface of the channel region and a doping concentration at a central region of the channel region are different from each other in the at least one second epitaxial layer. After the at least one first epitaxial layer is removed from the channel region, the at least one second epitaxial layer in the channel region serves as at least one nanowire. A gate surrounding the at least one nanowire is formed.
    Type: Application
    Filed: September 5, 2019
    Publication date: October 22, 2020
    Inventors: Huaxiang YIN, Jiaxin YAO, Qingzhu ZHANG, Zhaohao ZHANG, Tianchun YE
  • Publication number: 20200328309
    Abstract: A negative capacitance field effect transistor (NCFET) and a manufacturing method thereof. The NCFET includes: a substrate structure, including a MOS region; a gate insulating dielectric structure, covering the MOS region; and a metal gate stack layer, covering the gate insulating dielectric structure. The gate insulating dielectric structure includes an interface oxide layer, a HfO2 layer, a doping material layer, and a ferroelectric material layer, which are sequentially stacked along a direction away from the substrate structure. A ferroelectric material in the ferroelectric material layer is HfxA1-xO2, A represents a doping element, and 0.1?x?0.9. A material forming the doping material layer is AyOz or A, and a ratio of y/z is equal to 1/2, 2/3, 2/5 or 1/1. Ferroelectric characteristics, material stability, and material reliability of the NCFET are improved by increasing domain polarity of the ferroelectric material.
    Type: Application
    Filed: December 19, 2019
    Publication date: October 15, 2020
    Inventors: Huaxiang YIN, Qingzhu ZHANG, Zhaohao ZHANG, Tianchun YE
  • Publication number: 20200211910
    Abstract: A multilayer MOS device and a method for manufacturing the same. The manufacturing method includes: providing a MOS device including n layers, where n is a natural number greater than zero; forming a semiconductor layer on the MOS device including n layers; forming a gate oxide layer and a dummy gate on the semiconductor layer sequentially, where at least a part of the gate oxide layer is located between the dummy gate and the semiconductor layer; forming a metal silicide layer in the semiconductor layer at two sides of the dummy gate, to obtain a MOS device of an (n+1)-th layer, where the metal silicide layer serves as a metallized source-drain region or the metal silicide layer is doped to form a metalized source-drain region; and connecting a MOS device of an n-th layer of the n layers with the MOS device of the (n+1)-th layer via metallic interconnection.
    Type: Application
    Filed: December 20, 2019
    Publication date: July 2, 2020
    Inventors: Huaxiang YIN, Qingzhu ZHANG, Xiang LIN
  • Patent number: 10096691
    Abstract: A method for forming a metal silicide. The method comprises: providing a substrate having a fin, a gate formed on the fin, and spacers formed on opposite sides of the gate; depositing a Ti metal layer; siliconizing the Ti metal layer; and removing unreacted Ti metal layer. As the Ti atoms have relatively stable characteristics, diffusion happens mostly to Si atoms while the Ti atoms rarely diffuse during the thermal annealing. As a result, current leakage can be prevented in a depletion region and thus leakage current of the substrate can be reduced.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: October 9, 2018
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Qingzhu Zhang, Lichuan Zhao, Xiongkun Yang, Huaxiang Yin, Jiang Yan, Junfeng Li, Tao Yang, Jinbiao Liu
  • Publication number: 20160268391
    Abstract: A method for forming a metal silicide. The method comprises: providing a substrate having a fin, a gate formed on the fin, and spacers formed on opposite sides of the gate; depositing a Ti metal layer; siliconizing the Ti metal layer; and removing unreacted Ti metal layer. As the Ti atoms have relatively stable characteristics, diffusion happens mostly to Si atoms while the Ti atoms rarely diffuse during the thermal annealing. As a result, current leakage can be prevented in a depletion region and thus leakage current of the substrate can be reduced.
    Type: Application
    Filed: July 29, 2015
    Publication date: September 15, 2016
    Inventors: Qingzhu ZHANG, Lichuan ZHAO, Xiongkun YANG, Huaxiang YIN, Jiang YAN, Junfeng LI, Tao YANG, Jinbiao LIU
  • Patent number: 9373622
    Abstract: An CMOS device comprises a plurality of NMOS transistors and a plurality of PMOS transistors, each of which comprises a gate stack constituted of a gate insulating layer and a gate metal layer on a substrate, a source/drain region in the substrate on both sides of the gate stack and a channel region below the gate stack, wherein the gate metal layer of each NMOS transistor comprising a first barrier layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the gate metal layer of each PMOS transistor comprising a first barrier layer, a PMOS work function adjusting layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the first barrier layer in the gate metal layer of the NMOS transistor and the first barrier layer in the gate metal layer of the PMOS transistor contain a doping ion to finely adjust the work function.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: June 21, 2016
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huaxiang Yin, Hong Yang, Qingzhu Zhang, Qiuxia Xu