Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes determining delay windows for connections in a routing of a design for a PLD, identifying invalid connections in the routing based, at least in part, on the determined delay windows, and routing the invalid connections using a dual wave maze routing process to provide a delay-specific routing for the design. The delay-specific routing may be used to generate configuration data to configure physical components of the PLD, and the configuration data may be used to program the PLD to conform to the timing constraints of the design and/or PLD.

Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes determining delay windows for connections in a routing of a design for a PLD, identifying invalid connections in the routing based, at least in part, on the determined delay windows, and routing the invalid connections using a dual wave maze routing process to provide a delay-specific routing for the design. The delay-specific routing may be used to generate configuration data to configure physical components of the PLD, and the configuration data may be used to program the PLD to conform to the timing constraints of the design and/or PLD.

Abstract: Various techniques are provided to route connections within a programmable logic device (PLD). In one example, a method includes determining timing slacks for connections described in a netlist for a programmable logic device (PLD). The method also includes determining a plurality of priority groups. The connections are associated with one or more of the priority groups based on the timing slacks. The method also includes routing the connections associated with each priority group, from a highest priority group to a lowest priority group. Each priority group is iteratively routed to remove routing conflicts before lower priority groups are routed. Additional methods, systems, machine-readable mediums, and other techniques are also provided.

Abstract: Various techniques are provided to route connections within a programmable logic device (PLD). In one example, a method includes determining timing slacks for connections described in a netlist for a programmable logic device (PLD). The method also includes determining a plurality of priority groups. The connections are associated with one or more of the priority groups based on the timing slacks. The method also includes routing the connections associated with each priority group, from a highest priority group to a lowest priority group. Each priority group is iteratively routed to remove routing conflicts before lower priority groups are routed. Additional methods, systems, machine-readable mediums, and other techniques are also provided.

Abstract: Various techniques are provided for routing signals to pins of components of programmable logic devices (PLDs). In one example, a computer-implemented method of routing signals in a PLD includes routing a plurality of signals to pins of a component of the PLD. At least two of the signals are routed to a same pin. The method also includes, for each of the signals routed to the same pin, determining a cost value associated with each of two or more pins. the method also includes, for each of the signals routed to the same pin, rerouting the signal to one of the two or more pins having the lowest cost value. The method also includes repeating the determining a cost value and the rerouting until no more than one signal is routed to a pin.