Abstract: Embodiments of the present disclosure provide a method and an apparatus for displaying a business object in a video image and an electronic device. The method for displaying a business object in a video image includes: detecting at least one target object from a video image, and determining a feature point of the at least one target object; determining a display position of a to-be-displayed business object in the video image according to the feature point of the at least one target object; and drawing the business object at the display position by using computer graphics. According to the embodiments of the present disclosure, the method and apparatus are conductive to saving network resources and system resources of a client.

Abstract: The present invention provides a wafer level chip size package having cavities within which micro-machined parts are free to move, allowing access to electrical contacts, and optimized for device performance. Also a method for fabricating a wafer level chip size package for MEMS devices is disclosed. This packaging method provides a well packed device with the size much closely to the original one, making it possible to package the whole wafer at the same time and therefore, saves the cost and cycle time.

Abstract: The present invention disclosed a wafer level chip size packaged chip device with a double-layer lead structure and methods of fabricating the same. The double-layer lead is designed to meet a tendency of increasing quantity per area of peripheral arrayed compatible pads on a semiconductor chip, and also to save more space for layout of lead on the chip bottom surface for avoiding potential short inbetween which happen in increasing probability with increasing quantity per area on the condition of one-layer lead.

Abstract: The present invention provides patterned leads for a wafer level chip size package and methods for fabricating the same. The patterned leads include connection leads and solder pads. In designing, a compensation pattern is disposed on the connection lead or on the solder pad, so as to increase the distance between the connection lead and the solder pad. The present invention meets a tendency of increasing quantity per area of peripheral arrayed compatible pads and solder bumps on a semiconductor chip, and also saves more space for layout of leads on the chip bottom surface so as to avoid potential short circuit in between which happens in increasing probability with increasing quantity per area on the condition of the lead and the solder bump.

Abstract: The present invention provides a wafer level optical waveguide and a method for manufacturing the same, wherein it can be realized by employing manufacture process for semiconductor integrated circuits to manufacture a micron optical waveguide with a smooth interface, uniform thickness and a mirror-like end with any angle, and to remarkably reduce its manufacture cost at the meantime.

Abstract: The present invention provides a wafer level optical waveguide and a method for manufacturing the same, wherein it can be realized by employing manufacture process for semiconductor integrated circuits to manufacture a micron optical waveguide with a smooth interface, uniform thickness and a mirror-like end with any angle, and to remarkably reduce its manufacture cost at the meantime.

Abstract: The present invention provides a wafer level chip size package having cavities within which micro-machined parts are free to move, allowing access to electrical contacts, and optimized for device performance. Also a method for fabricating a wafer level chip size package for MEMS devices is disclosed. This packaging method provides a well packed device with the size much closely to the original one, making it possible to package the whole wafer at the same time and therefore, saves the cost and cycle time.

Abstract: The present invention provide a wafer level chip size packaged chip device with a N-shape junction at which external leads electrically connect to peripheral arrayed compatible pads and a method of fabricating the same. In the wafer level chip size package, with such an n-shape junction instead of a conventional T-shape junction observed in Shellcase type wafer level chip size package technology, electrical connections between compatible pads and external leads are more reliable due to larger connection area than the counterpart in the T-shape junction.

Abstract: The present invention disclosed a wafer level chip size packaged chip device with a double-layer lead structure and methods of fabricating the same. The double-layer lead is designed to meet a tendency of increasing quantity per area of peripheral arrayed compatible pads on a semiconductor chip, and also to save more space for layout of lead on the chip bottom surface for avoiding potential short inbetween which happen in increasing probability with increasing quantity per area on the condition of one-layer lead.

Abstract: The present invention provide a wafer level chip size packaged chip device with a N-shape junction at which external leads electrically connect to peripheral arrayed compatible pads and a method of fabricating the same. In the wafer level chip size package, with such an n-shape junction instead of a conventional T-shape junction observed in Shellcase type wafer level chip size package technology, electrical connections between compatible pads and external leads are more reliable due to larger connection area than the counterpart in the T-shape junction.