Abstract: A wafer-level heterogeneous dies integration structure and method are provided. The integration structure includes a wafer substrate, a silicon interposer, heterogeneous dies, and a configuration substrate. A standard integration module is defined by the heterogeneous dies connected to the silicon interposer. The standard integration module is connected to an upper surface of the wafer substrate, and the configuration substrate is connected to a lower surface of the wafer substrate. The wafer substrate is connected to the configuration substrate via Through Silicon Vias on lower surface of the wafer substrate. And the upper surface of the wafer substrate is provided with Re-distributed Layers and a standardized micro bump array to form standard integration zone connected to the standard integration module.

Abstract: A wafer-level heterogeneous dies integration structure and method are provided. The integration structure includes a wafer substrate, a silicon interposer, heterogeneous dies, and a configuration substrate. A standard integration module is defined by the heterogeneous dies connected to the silicon interposer. The standard integration module is connected to an upper surface of the wafer substrate, and the configuration substrate is connected to a lower surface of the wafer substrate. The wafer substrate is connected to the configuration substrate via Through Silicon Vias on lower surface of the wafer substrate. And the upper surface of the wafer substrate is provided with Re-distributed Layers and a standardized micro bump array to form standard integration zone connected to the standard integration module.

Abstract: A system-on-wafer structure and a fabrication method. The structure includes a wafer substrate, an integrated chiplet, a system configuration board and a thermal module. The wafer substrate and the integrated chiplet are bonded through a wafer micro bump array and a chiplet micro bump array. The wafer substrate and the system configuration board are bonded through a copper pillar array on wafer substrate topside and a pad on system configuration board backside. A molding layer is provided between the wafer substrate and the system configuration board, and is configured to mold the wafer substrate, the integrated chiplet and the copper pillar array. Integrated chiplet are electrically connected to each other through a re-distributed layer in wafer substrate. The integrated chiplet is electrically connected to the system configuration board through the re-distributed layer and the copper pillar array. The thermal module is attached to the backside of the wafer substrate.

Abstract: A routing structure and a method of a wafer substrate with standard integration zone for integration on-wafer, which comprises a core voltage network, an interconnection signal network, a clock signal network and a ground network, wherein the core voltage network and the interconnection signal network belong to a top metal layer, the clock signal network is located in a inner metal layer, and the ground network is located in a bottom metal layer. The pins provided on the standard zone include core voltage pins, interconnection signal pins, clock signal pins, ground pins, and complex function pins. The complex function pins are directly connected to the outside of the system by TSV at the bottom of the wafer, and the other pins are connected by their signal networks. The present disclosure solves the yield problem with few metal layers of the wafer substrate for SoW.

Abstract: A system-on-wafer structure and a fabrication method. The structure includes a wafer substrate, an integrated chiplet, a system configuration board and a thermal module. The wafer substrate and the integrated chiplet are bonded through a wafer micro bump array and a chiplet micro bump array. The wafer substrate and the system configuration board are bonded through a copper pillar array on wafer substrate topside and a pad on system configuration board backside. A molding layer is provided between the wafer substrate and the system configuration board, and is configured to mold the wafer substrate, the integrated chiplet and the copper pillar array. Integrated chiplet are electrically connected to each other through a re-distributed layer in wafer substrate. The integrated chiplet is electrically connected to the system configuration board through the re-distributed layer and the copper pillar array. The thermal module is attached to the backside of the wafer substrate.

Abstract: Provided is an input/output system applied to a network security defense system. A structural encoding unit and an error correction decoding unit are divided. The structure encoding unit is divided into input branch module and an input proxy module; and the error correction decoding unit is divided into an output routing module, an output proxy module, an adjudication branch module, an adjudication proxy module and a voting module. The input branch module is used for duplicating and distributing messages, the arbitration branch module is used for duplicating and distributing data, the voting module is used for performing voting, and the output routing module is used for selecting an output result from processing results of the output proxy module according to a voting result of the voting module.

Abstract: Provided are a security defense method and apparatus applied to a network security defense system. The method includes: using memoryless technology in a cyberspace information system, where the memoryless technology includes technology which is not affected by generalized disturbance; eliminating a memory of the cyberspace information system on an effect of random disturbance by using a redundancy and replacement mechanism; and eliminating a memory of the cyberspace information system on an effect of non-random disturbance by eliminating a memory of a program running in the cyberspace information system and/or data in the cyberspace information system. The present solution can block a memory of the cyberspace information system on an error caused by the generalized disturbance including the non-random disturbance and the random disturbance, thereby improving security of the cyberspace information system.

Abstract: A method for automatically sensing attack behaviors, the method including: distributing a service request from a network switch to a response module, where the response module includes a main controller configured for data interaction processing and an auxiliary controller configured for interactive data processing; generating, by the main controller and the auxiliary controller in the response module, respective response data according to the service request, respectively; and comparing the respective response data of the main controller with the respective response data of the auxiliary controller; if a result of comparison is inconsistent, indicating the network switch is abnormal, an administrator is informed, and the response data generated by the auxiliary controller is fed back to the network switch; and, if the result of comparison is consistent, the response data generated by the main controller is fed back to the network switch.

Abstract: A method for automatically sensing attack behaviors, the method including: distributing a service request from a network switch to a response module, where the response module includes a main controller configured for data interaction processing and an auxiliary controller configured for interactive data processing; generating, by the main controller and the auxiliary controller in the response module, respective response data according to the service request, respectively; and comparing the respective response data of the main controller with the respective response data of the auxiliary controller; if a result of comparison is inconsistent, indicating the network switch is abnormal, an administrator is informed, and the response data generated by the auxiliary controller is fed back to the network switch; and, if the result of comparison is consistent, the response data generated by the main controller is fed back to the network switch.

Abstract: The present disclosure provides a software-defined interconnection method and apparatus for heterogeneous protocol data, including: determining ports respectively corresponding to multiple network node devices connected with a software-definable network switching device; configuring each of the ports corresponding to a respective network node device according to a protocol type corresponding to the network node device, to obtain the first configuration information, and configure a port rate of the port according to a transmission rate of data of the network node devices, to obtain the second configuration information; receiving a data packet sent by the connected network node device through each of the ports; determining whether protocol conversion needs to be performed according to the protocol type of the destination port of the data packet, wherein if needed, the data packet sent from the port is encapsulated into the protocol type of the destination port, and sent to the destination port.

Abstract: A method and an apparatus for forwarding a heterogeneous protocol message, and a network switching device are provided, the method includes: receiving a network message; parsing the network message to obtain a destination address of the network message; looking up in a preset forwarding table a port corresponding to the destination address and a first protocol corresponding to the port; judging whether the first protocol matches a second protocol of the network message; performing, if not, protocol conversion on the network message in accordance with a preset conversion rule, so that the protocol type of the network message matches the port; forwarding the protocol-converted network message through the port. In the present disclosure, protocol conversion can be performed on messages from different protocol networks, so that the network switching device implements communication between different networks, and has a flexible protocol processing mode and powerful scalability.

Abstract: The present invention discloses a software/hardware device with uncertain service function and structural characterization and a method for scheduling the same. The device comprises a policy generator, a scheduler and a plurality of heterogeneous functional equivalents with equivalent functions, wherein, the policy generator is configured for providing a scheduling policy for the heterogeneous functional equivalents to the scheduler; the scheduler is configured for receiving an external service request, determining heterogeneous functional equivalents that provide a service to the external service request according to the scheduling policy given by the policy generator, assigning the service request to the determined heterogeneous functional equivalents, and outputting a service response which has an uncertain relation with uncertain structural characterization according to a feedback and the scheduling policy given by the policy generator.

Abstract: The present invention discloses a software/hardware device with uncertain service function and structural characterization and a method for scheduling the same. The device comprises a policy generator, a scheduler and a plurality of heterogeneous functional equivalents with equivalent functions, wherein, the policy generator is configured for providing a scheduling policy for the heterogeneous functional equivalents to the scheduler; the scheduler is configured for receiving an external service request, determining heterogeneous functional equivalents that provide a service to the external service request according to the scheduling policy given by the policy generator, assigning the service request to the determined heterogeneous functional equivalents, and outputting a service response which has an uncertain relation with uncertain structural characterization according to a feedback and the scheduling policy given by the policy generator.