Abstract: Aspects of the present disclosure provide for a method. In at least some examples, the method includes controlling gate terminals of one or more transistors of a charger to operate the charger in a buck-boost mode of operation to generate a system voltage based on a bus voltage by performing power conversion through switching, determining that the bus voltage is greater in value than a voltage of a battery coupled to the charger, and controlling the gate terminals of the one or more transistors of the charger to operate the charger in a pass-through mode of operation to generate the system voltage based on the bus voltage without performing power conversion.

Abstract: A device for charging battery cells has conductive lines to be coupled to the battery cells, a charge control circuit coupled to the conductive lines to charge the battery cells, and to determine voltages of the battery cells, and switches to balance the voltages among the battery cells. In operation, the charge control circuit charges the battery cells while determining the voltages of the battery cells, and suspends from charging the battery cells before determining the voltages of the battery cells in a second stage.

Abstract: In an example, a circuit comprising a first inductor coupled between a first node and a second node, a first PMOS having a source terminal coupled to the second node and a drain terminal coupled to a third node, a second PMOS having a source terminal coupled to a ground voltage potential and a drain terminal coupled to the second node, a third PMOS having a source terminal coupled to a fourth node and a drain terminal coupled to the third node, a fourth PMOS having a source terminal coupled to the ground voltage potential and a drain terminal coupled to the fourth node, a NMOS having a source terminal coupled to the third node and a drain terminal coupled to a fifth node, a second inductor coupled between the fourth node and the fifth node, and a controller.

Abstract: A device for charging battery cells has conductive lines to be coupled to the battery cells, a charge control circuit coupled to the conductive lines to charge the battery cells, and to determine voltages of the battery cells, and switches to balance the voltages among the battery cells. In operation, the charge control circuit charges the battery cells while determining the voltages of the battery cells, and suspends from charging the battery cells before determining the voltages of the battery cells in a second stage.

Abstract: Aspects of the present disclosure provide for a method. In at least some examples, the method includes controlling gate terminals of one or more transistors of a charger to operate the charger in a buck-boost mode of operation to generate a system voltage based on a bus voltage by performing power conversion through switching, determining that the bus voltage is greater in value than a voltage of a battery coupled to the charger, and controlling the gate terminals of the one or more transistors of the charger to operate the charger in a pass-through mode of operation to generate the system voltage based on the bus voltage without performing power conversion.

Abstract: In an example, a circuit comprising a first inductor coupled between a first node and a second node, a first PMOS having a source terminal coupled to the second node and a drain terminal coupled to a third node, a second PMOS having a source terminal coupled to a ground voltage potential and a drain terminal coupled to the second node, a third PMOS having a source terminal coupled to a fourth node and a drain terminal coupled to the third node, a fourth PMOS having a source terminal coupled to the ground voltage potential and a drain terminal coupled to the fourth node, a NMOS having a source terminal coupled to the third node and a drain terminal coupled to a fifth node, a second inductor coupled between the fourth node and the fifth node, and a controller.

Abstract: A method includes detecting removal or depletion of a power supply associated with a powered device. The powered device is configured to receive power from a power adapter via a narrow-voltage direct current/direct current (NVDC) charger and from the power supply. The method also includes, in response to the detection, disabling a dynamic power management function of the NVDC charger. The method further includes monitoring input current or input power provided to the powered device by the NVDC charger and determining if the input current or input power exceeds a threshold. In addition, the method includes, if the input current or input power exceeds the threshold, triggering a throttling of an operating clock frequency of the powered device. The method could also include (i) disabling a specified mode of operation and turning on a voltage regulator of the NVDC charger in response to the detection and (ii) providing over-voltage protection.

Abstract: Methods, electronic devices and USB charger apparatus are presented for fast USB charging, in which a high voltage master of the device detects a connected high voltage charger and selectively connects a current circuit to source or sink a current to or from one USB cable data signal conductor while providing a non-zero voltage to the other USB cable data signal conductor to configure the charger apparatus to provide charging power at a particular high voltage level above a nominal voltage level.

Abstract: Methods, electronic devices and USB charger apparatus are presented for fast USB charging, in which a high voltage master of the device detects a connected high voltage charger and selectively connects a current circuit to source or sink a current to or from one USB cable data signal conductor while providing a non-zero voltage to the other USB cable data signal conductor to configure the charger apparatus to provide charging power at a particular high voltage level above a nominal voltage level.

Abstract: A method includes detecting removal or depletion of a power supply associated with a powered device. The powered device is configured to receive power from a power adapter via a narrow-voltage direct current/direct current (NVDC) charger and from the power supply. The method also includes, in response to the detection, disabling a dynamic power management function of the NVDC charger. The method further includes monitoring input current or input power provided to the powered device by the NVDC charger and determining if the input current or input power exceeds a threshold. In addition, the method includes, if the input current or input power exceeds the threshold, triggering a throttling of an operating clock frequency of the powered device. The method could also include (i) disabling a specified mode of operation and turning on a voltage regulator of the NVDC charger in response to the detection and (ii) providing over-voltage protection.

Abstract: A power supply system and method for operating same. The power supply system is connectable to receive power from an adapter and supply power to a load. The power supply system includes a rechargeable battery, a buck mode circuit, and a boost mode circuit. A switching circuit switches between the buck mode circuit and boost mode circuit for supplying power to the load. If the power required by the load reaches a first predetermined level related to an adapter overload condition for a first predetermined time, the switching circuit disconnects said buck mode circuit from the load and connects the rechargeable battery and the boost mode circuit to said load. The first predetermined level may be established by a first predetermined percent of the current of a dynamic power management level established by the load, which is related to a power level below that which can be provided by the adapter.

Abstract: Two transistors of a class D output stage are driven by complementary, variable duty cycle signals PWM+ and PWM?. When the pulse width of the PWM+ signal becomes too narrow for reliable operation of prior art over-current protection circuits sensing the drain to source voltage of FET1 driven by PWM+, a Narrow Pulse Detector generates a signal indicative of this narrow pulse condition. A Negative Current Sense circuit measures the drain to source voltage across FET2 during the much longer conduction time of FET2 driven by PWM?. Because of the energy stored in the series inductor coupled to the output of the class D stage, a negative current flows through this FET2 during its conduction time. The resulting drain to source voltage of FET2 is measured and compared to a threshold. If the voltage indicative of current is over the threshold, and the Narrow Pulse Detector output indicates a narrow pulse condition, then an inhibit signal is generated which reduces current.

Abstract: A system for detecting a direct current (DC) component of a pulse-width modulated (PWM) signal includes a modulator configured to provide at least one PWM signal to an input of an amplifier. A DC detector is configured to detect a DC component of a selected one of the at least one PWM signal as a function of a switching frequency of the selected PWM signal. The DC detector provides at least one report signal that indicates a level of the DC component of the selected PWM signal relative to a predetermined threshold.

Abstract: A system and method is provided for providing integrated over-current protection in a switching power supply. In one embodiment, a switching power supply could comprise a gate drive circuit operative to receive a pulse-width modulated (PWM) signal and to drive at least one power field effect transistor (FET) between alternating activated and deactivated states based on a pulse-width of the PWM signal. The switching power supply could also comprise a current sense circuit operative to measure a current associated with the at least one power FET during the activated state. The switching power supply could also comprise a first over-current protection circuit providing a first adjustment to the PWM signal in response to the current being substantially between a first threshold and a second threshold. The second threshold could be greater than the first threshold.

Abstract: Two transistors of a class D output stage are driven by complementary, variable duty cycle signals PWM+ and PWM?. When the pulse width of the PWM+ signal becomes too narrow for reliable operation of prior art over-current protection circuits sensing the drain to source voltage of FET1 driven by PWM+, a Narrow Pulse Detector generates a signal indicative of this narrow pulse condition. A Negative Current Sense circuit measures the drain to source voltage across FET2 during the much longer conduction time of FET2 driven by PWM?. Because of the energy stored in the series inductor coupled to the output of the class D stage, a negative current flows through this FET2 during its conduction time. The resulting drain to source voltage of FET2 is measured and compared to a threshold. If the voltage indicative of current is over the threshold, and the Narrow Pulse Detector output indicates a narrow pulse condition, then an inhibit signal is generated which reduces current.

Abstract: A system for detecting a direct current (DC) component of a pulse-width modulated (PWM) signal includes a modulator configured to provide at least one PWM signal to an input of an amplifier. A DC detector is configured to detect a DC component of a selected one of the at least one PWM signal as a function of a switching frequency of the selected PWM signal. The DC detector provides at least one report signal that indicates a level of the DC component of the selected PWM signal relative to a predetermined threshold.

Abstract: An apparatus for controlling a power converter operating in response to a modulating signal during successive switching cycles includes: (a) A signal sensor coupled with the converter and sensing an extant signal during the extant cycle. (b) A signal level predictor coupled for receiving a reference signal and establishing a predicted level for the extant switching cycle. (c) A comparer coupled with the signal sensor and the signal level predictor for presenting a first output signal when the extant signal and the predicted signal level have a first relationship and for presenting a second output signal when the extant signal and the predicted signal level have a second relationship. (d) A control unit coupled with the comparer and with the converter for interrupting presentation of the modulating signal to the converter device when the comparing unit presents a selected one of the first and second output signals.

Abstract: An apparatus for controlling a power converter operating in response to a modulating signal during successive switching cycles includes: (a) A signal sensor coupled with the converter and sensing an extant signal during the extant cycle. (b) A signal level predictor coupled for receiving a reference signal and establishing a predicted level for the extant switching cycle. (c) A comparer coupled with the signal sensor and the signal level predictor for presenting a first output signal when the extant signal and the predicted signal level have a first relationship and for presenting a second output signal when the extant signal and the predicted signal level have a second relationship. (d) A control unit coupled with the comparer and with the converter for interrupting presentation of the modulating signal to the converter device when the comparing unit presents a selected one of the first and second output signals.

Abstract: A method and apparatus is provided to generate a pulse-width modulated (PWM) with enhanced features in accordance with a pre-determined protocol using a standard microprocessor. The method and apparatus is able to handle both variable on/off-timing control and multiple-event interrupts. The PWM functions of the present invention are implemented by software in the microprocessor that handles not only on/off events controlled by external pins, but is programmable on/off timing as well.

Abstract: A high resolution pulse width modulation (PWM) or voltage controlled output (DCO) generator is disclosed. The resolution is increased over that of the circuit clock by delaying the generated signal through a series of delays, all of which are controlled by a delay locked loop. The delays are a small fraction of the clock period, thus providing resolution greater than that of the circuit clock.