Abstract: The present disclosure provides a memory block and its control method. The method includes: performing row-selection operation on at least a portion of at least one row of multiple rows of word lines in the memory block to select at least a portion of at least one row of memory cells; performing column-selection operation on at least one column of memory cells of at least one of multiple memory subarrays to select at least one memory cells to perform a memory operation.

Abstract: A three-dimensional (3D) integrated circuit (IC) module and a method of fabricating the 3D IC module are disclosed. In the 3D IC module, a conductive hole for connection with an internal specified metal layer and a trench arranged to avoid the conductive hole are formed in a topmost substrate of a semiconductor structure. A first passivation layer spans over and covers the trench, the first passivation layer and the trench together delimit a heat exchange channel. During operation of 3D IC module, a heat dissipation medium may be caused to flow through the heat exchange channel to facilitate heat dissipation. Thus, the 3D IC module has enhanced heat dissipation ability and is substantially immune from the problems of excessive heat build-up and uneven heat dissipation. This helps optimize performance and reliability of the 3D IC module. The method can be used to make such a 3D IC module.

Abstract: A method of handling a test pad and a method of fabricating a semiconductor device are disclosed. The method of handling a test pad includes: providing a substrate formed thereon with a first insulating dielectric layer and a first test pad in the first insulating dielectric layer, wherein a surface of the first test pad is at least partially exposed from the first insulating dielectric layer, and there is a probe mark with a protrusion resulting from testing with probe tips on the surface portion of the first test pad exposed from the first insulating dielectric layer; and heating and melting the protrusion by laser annealing, thereby reducing a height of the protrusion. This invention can ensure good flatness of a surface to be bonded while enabling reduced process complexity and preventing metal contamination of the surface to be bonded.

Abstract: A method of fabricating an IC device is disclosed, in which a dielectric layer is first etched to form a contact opening and a dummy opening. Both do not extend through the dielectric layer, the contact opening has a width greater than that of the dummy opening. A sacrificial layer, which covers inner surface of the dummy opening and the dielectric layer at side surface of the contact opening, and from which the dielectric layer at bottom surface of the contact opening is exposed, is then formed, and under protection of this sacrificial layer, the dielectric layer exposed in the contact opening is etched in a self-aligned manner, a self-aligned contact hole is formed, in which a surface of the conductive structure is exposed. In this way, reliability of a contact that extends in both contact opening and self-aligned contact hole is ensured, avoiding the problem of possible contact failure.

Abstract: Semiconductor structure, comprising a memory-array unit comprising: a substrate, a memory array disposed on the substrate, and a first bonding region disposed around the memory array. The memory array comprises multiple word lines, multiple bit lines, and multiple source lines. The first bonding region comprises a first substrate-connecting bonding region, a first bit-line bonding region, a first word-line bonding region, and a first source-line bonding region. The first substrate-connecting bonding region is configured to connect the substrate electrically to a surface of the memory-array unit, the first bit-line bonding region is configured to connect the bit lines electrically to the surface of the memory-array unit, the first word-line bonding region is configured to connect the word lines electrically to the surface of the memory-array unit, and the first source-line bonding region is configured to connect the source lines electrically to the surface of the memory-array unit.

Abstract: A method of fabricating an IC device is disclosed, in which a dielectric layer is first etched to form a contact opening and a dummy opening. Both do not extend through the dielectric layer, the contact opening has a width greater than that of the dummy opening. A sacrificial layer, which covers inner surface of the dummy opening and the dielectric layer at side surface of the contact opening, and from which the dielectric layer at bottom surface of the contact opening is exposed, is then formed, and under protection of this sacrificial layer, the dielectric layer exposed in the contact opening is etched in a self-aligned manner, a self-aligned contact hole is formed, in which a surface of the conductive structure is exposed. In this way, reliability of a contact that extends in both contact opening and self-aligned contact hole is ensured, avoiding the problem of possible contact failure.

Abstract: The present invention provides a large die, a method of forming the large die and a large die wafer. The method includes: providing a wafer containing a plurality of large dies each having a size greater than that of a maximum field of exposure of a stepper, each large die including at least two die portions to be stitched together, the die portions including a substrate and a first metal layer, the first metal layer including at least to-be-interconnected metal layers for interconnection of the die portions; and forming a second metal layer including at least inter-die interconnecting metal layers crossing dummy dicing margins between adjacent die portions and coming into electrical connection with the to-be-interconnected metal layers of the adjacent die portions. The present invention allows interconnection of the die portions to be stitched together in each large die.

Abstract: A vision system is provided which allows viewing and/or inspection of an end surface of an optical fiber through a bulkhead on a backplane of a rack. By placing such a vision system on a mount configured to be inserted in the rack, the use of such a vision system does not require the rack design be modified or that other modules be removed. Preferably an adapter for mating the vision system with the bulkhead may be moved to position the adapter relative to the bulkhead housing the fiber of interest.

Abstract: A system and method for inspecting an optical fiber, particularly an epoxy region of an optical fiber in a supporting structure. The inspection may use an initialization routine including determination of whether the centering between the optical fiber and the illumination source is sufficient. The meters used to determine completion of initialization may be displayed. The inspection may analyze the uniformity of the thickness of an epoxy layer between the fiber and the supporting structure. The inspection may also analyze the core and clad zones of the optical fiber for scratches and other intensity variations, referred to generically as blobs. The core zone preferably encompasses a region larger than the core alone, e.g., an area which is a multiple of the core diameter. Different criteria are established for the core and clad zones, with no discontinuities being tolerated in the core zone. Scratches may be extracted using a windowing technique.