Abstract: An approach for altering alter training data and training process associated with a neural network to emulate environmental noise and operational instrument error by using the concepts of shots to sample within a squeezed space model, wherein shots are an uncertainty index that is the average of all shots from a sampling, is disclosed. The approach leverages a squeeze theorem to create a squeezed space model based on the regression of the upper and lower bound associated with the environmental noise and instrument error. The approach calculates an average noise index based on the squeezed space model, wherein the index is used to alter the training data and process.

Abstract: An approach alerting users based on a detected defect during manufacturing quality inspection based on graphical images is disclosed. The approach initiates a device inspection, wherein a model controller collects metadata about a product to be inspected and select a first model with a highest score to identify defects in the device. The approach utilizes an API to obtain results from the inspection and after determining that another model is available, initiating the second model run via an edge device performing the inspection of the device. And the algorithm awaits a response in detecting a defect during either the first model run or the second model run, providing an alert detailing the defect detected in the device.

Abstract: An approach alerting users based on a detected defect during manufacturing quality inspection based on graphical images is disclosed. The approach initiates a device inspection, wherein a model controller collects metadata about a product to be inspected and select a first model with a highest score to identify defects in the device. The approach utilizes an API to obtain results from the inspection and after determining that another model is available, initiating the second model run via an edge device performing the inspection of the device. And the algorithm awaits a response in detecting a defect during either the first model run or the second model run, providing an alert detailing the defect detected in the device.

Abstract: A method, a computer system, and a computer program product for parallel conversion is provided. Embodiments of the present invention may include analyzing raw classical code using a code embedded deep learning model. Embodiments of the present invention may include analyzing running classical code using a deep learning model. Embodiments of the present invention may include marking a location of the raw classical code for a first quantum conversion. Embodiments of the present invention may include suggesting a memory size of the running classical code for a second quantum conversion. Embodiments of the present invention may include aggregating the raw classical code for the first quantum conversion. Embodiments of the present invention may include aggregating the running classical code for the second quantum conversion.

Abstract: A method, a computer system, and a computer program product for parallel conversion is provided. Embodiments of the present invention may include analyzing raw classical code using a code embedded deep learning model. Embodiments of the present invention may include analyzing running classical code using a deep learning model. Embodiments of the present invention may include marking a location of the raw classical code for a first quantum conversion. Embodiments of the present invention may include suggesting a memory size of the running classical code for a second quantum conversion. Embodiments of the present invention may include aggregating the raw classical code for the first quantum conversion. Embodiments of the present invention may include aggregating the running classical code for the second quantum conversion.

Abstract: An approach for altering alter training data and training process associated with a neural network to emulate environmental noise and operational instrument error by using the concepts of shots to sample within a squeezed space model, wherein shots are an uncertainty index that is the average of all shots from a sampling, is disclosed. The approach leverages a squeeze theorem to create a squeezed space model based on the regression of the upper and lower bound associated with the environmental noise and instrument error. The approach calculates an average noise index based on the squeezed space model, wherein the index is used to alter the training data and process.

Abstract: Individual health vulnerability is assessed by obtaining health risk prevalence level data containing health risk prevalence levels for one or more health risks over a given geographical area. The health risk prevalence level data to generate for each health risk a prevalence level forecast as a function of time and location. A health risk prevalence level map is generated for the given geographical area illustrating current and future health risk prevalence levels for each health risk at a plurality of locations within the given geographical area. Personal health status data are obtained for a given individual along with a proposed travel itinerary f covering at least a portion of the geographical area over a given time duration. The personal health status data, travel itinerary and map generate a personal health risk vulnerability model containing a quantification of vulnerability to the one or more health risks resulting from the travel itinerary.

Abstract: Individual health vulnerability is assessed by obtaining health risk prevalence level data containing health risk prevalence levels for one or more health risks over a given geographical area. The health risk prevalence level data to generate for each health risk a prevalence level forecast as a function of time and location. A health risk prevalence level map is generated for the given geographical area illustrating current and future health risk prevalence levels for each health risk at a plurality of locations within the given geographical area. Personal health status data are obtained for a given individual along with a proposed travel itinerary f covering at least a portion of the geographical area over a given time duration. The personal health status data, travel itinerary and map generate a personal health risk vulnerability model containing a quantification of vulnerability to the one or more health risks resulting from the travel itinerary.

Abstract: Individual health vulnerability is assessed by obtaining health risk prevalence level data containing health risk prevalence levels for one or more health risks over a given geographical area. The health risk prevalence level data to generate for each health risk a prevalence level forecast as a function of time and location. A health risk prevalence level map is generated for the given geographical area illustrating current and future health risk prevalence levels for each health risk at a plurality of locations within the given geographical area. Personal health status data are obtained for a given individual along with a proposed travel itinerary f covering at least a portion of the geographical area over a given time duration. The personal health status data, travel itinerary and map generate a personal health risk vulnerability model containing a quantification of vulnerability to the one or more health risks resulting from the travel itinerary.

Abstract: Individual health vulnerability is assessed by obtaining health risk prevalence level data containing health risk prevalence levels for one or more health risks over a given geographical area. The health risk prevalence level data to generate for each health risk a prevalence level forecast as a function of time and location. A health risk prevalence level map is generated for the given geographical area illustrating current and future health risk prevalence levels for each health risk at a plurality of locations within the given geographical area. Personal health status data are obtained for a given individual along with a proposed travel itinerary f covering at least a portion of the geographical area over a given time duration. The personal health status data, travel itinerary and map generate a personal health risk vulnerability model containing a quantification of vulnerability to the one or more health risks resulting from the travel itinerary.

Abstract: An embedded vertical optical grating, a semiconductor device including the embedded vertical optical grating and a method for forming the same. The method for forming the embedded optical grating within a substrate includes depositing a hard mask layer on the substrate, patterning at least one opening within the hard mask layer, vertically etching a plurality of scallops within the substrate corresponding to the at least one opening within the hard mask layer, removing the hard mask layer, and forming an oxide layer within the plurality of scallops to form the embedded vertical optical grating.

Abstract: A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.

Abstract: At least one gate dielectric, a gate electrode, and a gate cap dielectric are formed over at least one channel region of at least one semiconductor fin. A gate spacer is formed on the sidewalls of the gate electrode, exposing end portions of the fin on both sides of the gate electrode. The exposed portions of the semiconductor fin are vertically and laterally etched, thereby reducing the height and width of the at least one semiconductor fin in the end portions. Exposed portions of the insulator layer may also be recessed. A lattice-mismatched semiconductor material is grown on the remaining end portions of the at least one semiconductor fin by selective epitaxy with epitaxial registry with the at least one semiconductor fin. The lattice-mismatched material applies longitudinal stress along the channel of the finFET formed on the at least one semiconductor fin.

Abstract: A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.

Abstract: A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.

Abstract: At least one gate dielectric, a gate electrode, and a gate cap dielectric are formed over at least one channel region of at least one semiconductor fin. A gate spacer is formed on the sidewalls of the gate electrode, exposing end portions of the fin on both sides of the gate electrode. The exposed portions of the semiconductor fin are vertically and laterally etched, thereby reducing the height and width of the at least one semiconductor fin in the end portions. Exposed portions of the insulator layer may also be recessed. A lattice-mismatched semiconductor material is grown on the remaining end portions of the at least one semiconductor fin by selective epitaxy with epitaxial registry with the at least one semiconductor fin. The lattice-mismatched material applies longitudinal stress along the channel of the finFET formed on the at least one semiconductor fin.

Abstract: A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.

Abstract: NMOS and PMOS device structures with separately strained channel regions and methods of their fabrication are disclosed. The source and the drain of the NMOS device is epitaxially grown of a material which causes a shift in the strain of the NMOS device channel in the tensile direction. While, the source and the drain of the PMOS device is epitaxially grown of a material which causes a shift in the strain of the PMOS device channel in the compressive direction.

Abstract: A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.

Abstract: A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.