Abstract: Plasma processing apparatus for processing a workpiece are provided. In one example embodiment, a plasma processing apparatus for processing a workpiece includes a processing chamber, a plasma chamber separated from the processing, and an inductively coupled plasma source configured to generate a plasma in the plasma chamber. The apparatus includes a pedestal disposed within the processing chamber configured to support a workpiece. The apparatus includes an insert disposed in the plasma chamber movable to one or more vertical positions within the plasma chamber. Methods for processing of workpieces are also provided.

Abstract: Apparatus and methods for processing a workpiece using a plasma are provided. In one example implementation, an apparatus can include a processing chamber. The apparatus can include a plasma chamber comprising a dielectric tube defining a sidewall. The apparatus can include an inductively coupled plasma source. The inductively coupled plasma source can include an RF generator configured to energize an induction coil disposed about the dielectric tube. The apparatus can include a separation grid separating the processing chamber from the plasma chamber. The apparatus can include a controller configured to operate the inductively coupled plasma source in a pulsed mode. During the pulsed mode the RF generator is configured to apply a plurality of pulses of RF power to the induction coil. A frequency of pulses can be in a range of about 1 kHz to about 100 kHz.

Abstract: Method, materials and structures are described for the fabrication of dual damascene features in integrated circuits. In via-first dual damascene fabrication, a bottom-antireflective-coating (“BARC”) is commonly deposited into the via and field regions surrounding the via, 107. Subsequent trench etch with conventional etching chemistries typically results in isolated regions of BARC, 107a, surrounded by “fencing” material, 108, at the bottom of the via. Such fencing hinders conformal coating with barrier/adhesion layers and can reduce device yield. The present invention relates to the formation of a BARC plug, 107c, partially filling the via and having a convex upper surface, 400, prior to etching the trench. Such a BARC structure is shown to lead to etching without the formation of fencing and a clean dual damascene structure for subsequent coating.

Abstract: Method, materials and structures are described for the fabrication of dual damascene features in integrated circuits. In via-first dual damascene fabrication, a bottom-antireflective-coating (“BARC”) is commonly deposited into the via and field regions surrounding the via, 107. Subsequent trench etch with conventional etching chemistries typically results in isolated regions of BARC, 107a, surrounded by “fencing” material, 108, at the bottom of the via. Such fencing hinders conformal coating with barrier/adhesion layers and can reduce device yield. The present invention relates to the formation of a BARC plug, 107c, partially filling the via and having a convex upper surface, 400, prior to etching the trench. Such a BARC structure is shown to lead to etching without the formation of fencing and a clean dual damascene structure for subsequent coating.