Patents by Inventor Qiuhong Zou
Qiuhong Zou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8952512Abstract: A wafer-level package structure of a light emitting diode and a manufacturing method thereof are provided in the present invention. The wafer-level package structure of a light emitting diode includes a die, a first insulating layer, at least two wires, bumps, an annular second insulating layer on the wires and the insulating layer, the annular second insulating layer surrounding an area between the bumps and there being spaces arranged between the second insulating layer and the bumps; a light reflecting cup on the second insulating layer; at least two discrete lead areas and leads in the lead areas. The technical solution of the invention reduces the area required for the substrate; and the electrodes can be extracted in the subsequent structure of the package without gold wiring to thereby further reduce the volume of the package.Type: GrantFiled: April 19, 2013Date of Patent: February 10, 2015Assignee: China Wafer Level CSP Ltd.Inventors: Junjie Li, Wenbin Wang, Qiuhong Zou, Guoqing Yu, Wei Wang
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Publication number: 20130228817Abstract: A wafer-level package structure of a light emitting diode and a manufacturing method thereof are provided in the present invention. The wafer-level package structure of a light emitting diode includes a die, a first insulating layer, at least two wires, bumps, an annular second insulating layer on the wires and the insulating layer, the annular second insulating layer surrounding an area between the bumps and there being spaces arranged between the second insulating layer and the bumps; a light reflecting cup on the second insulating layer; at least two discrete lead areas and leads in the lead areas. The technical solution of the invention reduces the area required for the substrate; and the electrodes can be extracted in the subsequent structure of the package without gold wiring to thereby further reduce the volume of the package.Type: ApplicationFiled: April 19, 2013Publication date: September 5, 2013Applicant: CHINA WAFER LEVEL CSP LTD.Inventors: Junjie LI, Wenbin WANG, Qiuhong ZOU, Guoqing YU, Wei WANG
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Patent number: 8445919Abstract: A wafer-level package structure of a light emitting diode and a manufacturing method thereof, and the package structure includes: a die including a first side and a second side opposite to the first side; a first insulating layer on the first side of the die; at least two wires which are arranged on the insulating layer and electrically isolated from each other; bumps which are arranged on the wires and adapted to be electrically connected correspondingly with electrodes of a bare chip of the light emitting diode; at least two discrete lead areas on the second side of the die; and leads in the lead areas, electrically isolated from each other and electrically connected correspondingly with the wires.Type: GrantFiled: February 19, 2010Date of Patent: May 21, 2013Assignee: China Wafer Level CSP LtdInventors: Junjie Li, Wenbin Wang, Qiuhong Zou, Guoqing Yu, Wei Wang
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Patent number: 8174090Abstract: The invention discloses a packaging structure and packaging method. The packaging structure includes a solder bump, a pad located on a front side of a chip, and an intermediate metal layer which connects the solder bump and the pad, wherein a through hole passing from a back side of the chip to the pad is provided on the chip, and the intermediate metal layer is connected to the pad within the through hole. In the packaging structure, a through hole is formed on the back side of the chip to expose the pad on the front side of the chip and the intermediate metal layer is connected to the pad within the through hole. This provides a relatively large contacting area therebetween. The connection thus formed is more reliable and stable, compared with the prior art structure.Type: GrantFiled: May 1, 2009Date of Patent: May 8, 2012Assignee: China Wafer Level CSP Ltd.Inventors: Zhiqi Wang, Guoqing Yu, Qiuhong Zou, Youjun Wang, Wei Wang
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Publication number: 20110006322Abstract: A wafer-level package structure of a light emitting diode and a manufacturing method thereof, and the package structure includes: a die including a first side and a second side opposite to the first side; a first insulating layer on the first side of the die; at least two wires which are arranged on the insulating layer and electrically isolated from each other; bumps which are arranged on the wires and adapted to be electrically connected correspondingly with electrodes of a bare chip of the light emitting diode; at least two discrete lead areas on the second side of the die; and leads in the lead areas, electrically isolated from each other and electrically connected correspondingly with the wires.Type: ApplicationFiled: February 19, 2010Publication date: January 13, 2011Applicant: CHINA WAFER LEVEL CSP LTD.Inventors: Junjie LI, Wenbin WANG, Qiuhong ZOU, Guoqing YU, Wei WANG
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Publication number: 20100171134Abstract: The present invention relates to an optical converter and a manufacturing method thereof and a light emitting diode. An optical converter for a light emitting diode includes two substrates, in which, a annular first cavity wall is arranged between the two substrates, and an airtight space filled with an optical conversion substance is surrounded by the first cavity wall and the two substrates. The invention implements the encapsulation and manufacturing of the optical conversion substance for the LED. The structure and the manufacturing method according to the invention can be utilized to encapsulate an active optical conversion substance in the optical converter while avoiding the active optical conversion substance reacting to other active substance, e.g., oxygen, during manufacturing. Furthermore, the optical conversion substance is encapsulated with wafer level chip size packaging to thereby improve the efficiency of manufacturing the optical converter and reduce the cost.Type: ApplicationFiled: June 10, 2009Publication date: July 8, 2010Applicant: China Wafer Level CSP Ltd.Inventors: Mingda Shao, Junjie Li, Hanyu Li, Qiuhong Zou, Zhiqi Wang, Guoqing Yu, Youjun Wang, Wei Wang
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Publication number: 20100133640Abstract: The invention discloses a packaging structure and packaging method. The packaging structure includes a solder bump, a pad located on a front side of a chip, and an intermediate metal layer which connects the solder bump and the pad, wherein a through hole passing from a back side of the chip to the pad is provided on the chip, and the intermediate metal layer is connected to the pad within the through hole. In the packaging structure, a through hole is formed on the back side of the chip to expose the pad on the front side of the chip and the intermediate metal layer is connected to the pad within the through hole. This provides a relatively large contacting area therebetween. The connection thus formed is more reliable and stable, compared with the prior art structure.Type: ApplicationFiled: May 1, 2009Publication date: June 3, 2010Applicant: China Wafer Level CSP Ltd.Inventors: Zhiqi Wang, Guoqing Yu, Qiuhong Zou, Youjun Wang, Wei Wang
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Publication number: 20100065956Abstract: The application provides a packaging structure, a packaging method and a photosensitive device. The packaging structure includes a substrate structure, a chip and a solder bump electrically connecting with a pad on the chip. The solder bump is located on the substrate structure, so that the multilayer coverage structure required when forming a bump on a side of the chip in the prior art packaging structure is avoided. In this way, the thickness of the packaging structure is reduced and the reliably of the packaging structure is improved.Type: ApplicationFiled: March 27, 2009Publication date: March 18, 2010Inventors: Zhiqi WANG, Guoqing Yu, Qiuhong Zou, Wei Wang
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Publication number: 20090289317Abstract: The present invention provides a packaging structure and a method for fabricating the same, the packaging structure includes a chip, a compatible pad provided on the chip, an intermediate metal layer electrically connecting with the compatible pad, a solder bump, and a redistribution metal layer electrically connecting with the solder bump, wherein the redistribution metal layer connects with the intermediate metal layer directly to form an electrical connection. Also, some connections between the redistribution metal layer and the intermediate metal layer are in a manner of concave shape, while other connections between the redistribution metal layer and the intermediate metal layer are in a manner of “-” shape, so that the number of the connections increases while the stability of connection is ensured.Type: ApplicationFiled: September 19, 2008Publication date: November 26, 2009Inventors: Guoping YU, Zhiqi Wang, Guoqing Yu, Wei Wang, Qiuhong Zou