Abstract: A display module is provided. The display module includes: a display panel, a light control panel, at least one first circuit board for the display panel, and at least one second circuit board for the light control panel. The display panel and the light control panel are stacked, the display panel is on a light-emitting side of the light control panel, a light-emitting surface of the display panel is on a first surface, and at least part of an orthographic projection of any one of the at least one first circuit board on the first surface does not overlap with an orthographic projection of the at least one second circuit board on the first surface in a direction perpendicular to the first surface.

Abstract: A gate driving circuit and a display panel are provided. The gate driving circuit includes M shift registers and N clock signal lines; every N adjacent shift registers among the M shift registers are respectively connected to the N clock signal lines, where N is an even number greater than or equal to 4, and M is an integer greater than or equal to N; a signal output terminal (OUTPUT) of an ith shift register is connected to a signal input terminal (INPUT) of a (i+p)th shift register, where (N?4)/2?p?N/2, and i is taken from 1 to (M?p); and a pull-up reset signal terminal of a jth shift register is connected to a signal output terminal (OUTPUT) of a (j+q)th shift register, where 1<q?p<N/2, and j is taken from 1 to (M?q).

Abstract: An array substrate, a manufacturing method of the array substrate, and a touch display device are provided. Orthographic projections of the touch signal lines adjacent to each other included in a same touch signal line group on the base substrate are respectively provided on two sides of an orthographic projection of a same second signal line on the base substrate, each of the orthographic projections of the touch signal lines adjacent to each other and the orthographic projection of the same second signal line includes a portion provided between orthographic projections of the touch electrodes adjacent to each other on the base substrate, and a layer in which the touch signal lines adjacent to each other are provided is different from a layer in which the same second signal line is provided.

Abstract: A shift register unit includes a first pull-up node control circuit, a second pull-up node control circuit, a pull-down node control circuit, an output pull-up circuit and an output pull-down circuit. The first pull-up node control circuit is configured to control a first pull-up node to be electrically connected to a second voltage end under the control of an input signal, and control the first pull-up node to be electrically connected to a first voltage end under the control of a resetting signal. The second pull-up node control circuit is configured to control the second pull-up node to be electrically connected to the second voltage end under the control of the input signal applied to the input end, and control the second pull-up node to be electrically connected to the first voltage end under the control of the resetting signal from the resetting end.

Abstract: A display device and a method for bonding the display device are provided. The display device includes a display panel and a plurality of chip on films. The plurality of chip on films are arranged along a first edge of the display panel, and are divided into a plurality of groups of chip on films, and each group of chip on films includes at least two chip on films, and is bonded to the display panel through a same anisotropic conductive film.

Abstract: A display panel and a display device are disclosed. The display panel comprises an array substrate and spacers; the array substrate comprises a first substrate, gate lines, data lines, and multiple sub-pixel units; the first substrate is provided with multiple sub-pixel regions, first wiring regions each located between two adjacent rows of sub-pixel regions, and second wiring regions each located between two adjacent columns of sub-pixel regions and intersecting the first wiring regions; at least part of each sub-pixel unit is located on a sub-pixel region; the gate lines and the data lines are respectively located on the first wiring regions and the second wiring regions and are electrically connected to the sub-pixel units; the data lines and the gate lines are insulated from each other and intersect each other; each data line is provided with an alignment part.

Abstract: The embodiments of the present disclosure provide a display panel and a display apparatus. The display panel includes: a first substrate; a plurality of sub-pixels arranged in an array on the substrate, the plurality of sub-pixels comprising a first type of sub-pixels and a second type of sub-pixels; and at least one data line, each of which is disposed between adjacent columns of sub-pixels of the array and extending along a second direction, an overlapped area of projection of each data line on the first substrate and projection of the first type of sub-pixels on the first substrate has a first width, and an overlapped area of the projection of each data line on the first substrate and projection of the second type of sub-pixels on the first substrate has a second width less than the first width.

Abstract: An array substrate and a manufacturing method thereof, a display panel and a display device are provided. The array substrate includes common electrodes, multiple first common electrode lines and multiple second common electrode lines. The multiple first common electrode lines intersect with the multiple second common electrode lines to form grids. The multiple first common electrode lines are connected with the common electrodes through first via-holes and the multiple second common electrode lines are connected with the common electrodes through second via-holes.

Abstract: A gate driving circuit, a method for driving the gate driving circuit, and a display panel. The gate driving circuit includes N-stages of cascaded shift registers divided into at least one group of K-stages in which a clock signal terminal of a k-th stage of shift register is connected to receive a k-th clock signal, where N, k and K are positive integers, and 1?k?K?N; and an input signal terminal of a n-th stage of shift register is connected to an output signal terminal of a (n?i)-th stage of shift register, and reset signal terminals of the n-th and (n+1)-th stages of shift registers are connected to an output signal terminal of a (n+j)-th stage of shift register, wherein the n is one of an odd number and an even number, where i and j are positive integers, 1<n<N, (K?2)/2?i?K/2, and K/2<j?K?2.

Abstract: Embodiments of the present disclosure provide a method of driving display, and a display device. The method of driving display includes: scanning, progressively or rows by rows, a plurality of sub-pixels arranged in an N×M array, to turn on each row of sub-pixels scanned, so that a duration in which two adjacent rows of sub-pixels are simultaneously in an ON state is greater than or equal to two times a unit scanning time, wherein the unit scanning time is a time required for scanning a row of sub-pixels, N is an integer greater than 1, and M is an integer greater than 1; and applying data signals to at least two rows of sub-pixels simultaneously in the ON state, so that a duration of applying the data signals to each row of sub-pixels is greater than the unit scanning time.

Abstract: A shift register unit includes a first pull-up node control circuit, a second pull-up node control circuit, a pull-down node control circuit, an output pull-up circuit and an output pull-down circuit. The first pull-up node control circuit is configured to control a first pull-up node to be electrically connected to a second voltage end under the control of an input signal, and control the first pull-up node to be electrically connected to a first voltage end under the control of a resetting signal. The second pull-up node control circuit is configured to control the second pull-up node to be electrically connected to the second voltage end under the control of the input signal applied to the input end, and control the second pull-up node to be electrically connected to the first voltage end under the control of the resetting signal from the resetting end.

Abstract: A shift register unit includes a first pull-up node control circuit, a second pull-up node control circuit, a pull-down node control circuit, an output pull-up circuit and an output pull-down circuit. The first pull-up node control circuit is configured to control a first pull-up node to be electrically connected to a second voltage end under the control of an input signal, and control the first pull-up node to be electrically connected to a first voltage end under the control of a resetting signal and/or a voltage signal at a pull-down node. The second pull-up node control circuit is configured to control a second pull-up node to be electrically connected to an input end under the control of the input signal, and control the second pull-up node to be electrically connected to the first voltage end under the control of the resetting signal.

Abstract: The present disclosure provides a display substrate and a liquid crystal panel.

Abstract: A shift register unit includes a first pull-up node control circuit, a second pull-up node control circuit, a pull-down node control circuit, an output pull-up circuit and an output pull-down circuit. The first pull-up node control circuit is configured to control a first pull-up node to be electrically connected to a second voltage end under the control of an input signal, and control the first pull-up node to be electrically connected to a first voltage end under the control of a resetting signal and/or a voltage signal at a pull-down node. The second pull-up node control circuit is configured to control a second pull-up node to be electrically connected to an input end under the control of the input signal, and control the second pull-up node to be electrically connected to the first voltage end under the control of the resetting signal.

Abstract: A start signal generation circuit, a driving method and a display device are provided. The start signal generation circuit includes: a pull-down node control sub-circuit; a pull-up control node control sub-circuit, configured to control a potential of the pull-up control node under the control of voltage signals from a first clock signal input terminal, a second clock signal input terminal, and the 2nth clock signal input terminal; a pull-up node control sub-circuit; a storage sub-circuit, connected between the pull-up node PU and a start signal output terminal; and a start signal output sub-circuit, where n is an integer larger than 1, and smaller than or equal to N, N is an integer larger than 1.

Abstract: A start signal generation circuit, a driving method and a display device are provided. The start signal generation circuit includes: a pull-down node control sub-circuit; a pull-up control node control sub-circuit, configured to control a potential of the pull-up control node under the control of voltage signals from a first clock signal input terminal, a second clock signal input terminal, and the 2nth clock signal input terminal; a pull-up node control sub-circuit; a storage sub-circuit, connected between the pull-up node PU and a start signal output terminal; and a start signal output sub-circuit, where n is an integer larger than 1, and smaller than or equal to N, N is an integer larger than 1.

Abstract: An array substrate and a manufacturing method thereof, a display panel and a display device are provided. The array substrate includes common electrodes, multiple first common electrode lines and multiple second common electrode lines. The multiple first common electrode lines intersect with the multiple second common electrode lines to form grids. The multiple first common electrode lines are connected with the common electrodes through first via-holes and the multiple second common electrode lines are connected with the common electrodes through second via-holes.

Abstract: The embodiments of the present disclosure provide a display panel and a display apparatus. The display panel includes: a first substrate; a plurality of sub-pixels arranged in an array on the substrate, the plurality of sub-pixels comprising a first type of sub-pixels and a second type of sub-pixels; and at least one data line, each of which is disposed between adjacent columns of sub-pixels of the array and extending along a second direction, an overlapped area of projection of each data line on the first substrate and projection of the first type of sub-pixels on the first substrate has a first width, and an overlapped area of the projection of each data line on the first substrate and projection of the second type of sub-pixels on the first substrate has a second width less than the first width.

Abstract: An array substrate, a display panel and a display device are disclosed. The array substrate includes a base substrate and a plurality of pixel unit. Each of the pixel unit includes a thin-film-transistor, and the thin-film-transistor includes a gate electrode and a drain electrode; the drain electrode includes a first drain electrode portion, a second drain electrode portion and a first connection portion; and an orthographic projection of the first drain electrode portion on the base substrate and an orthographic projection of the gate electrode on the base substrate are spaced apart, and an orthographic projection of the second drain electrode portion on the base substrate and the orthographic projection of the gate electrode on the base substrate at least partially overlap.

Abstract: There are disclosed in the present disclosure a shift register unit and a driving method thereof, a gate driving circuit, an array substrate and a display apparatus. The shift register unit includes: an input sub-circuit for receiving an input signal from an input terminal, outputting the input signal to the pull-up node, and outputting a pull-up signal through the pull-up node; a first output sub-circuit for receiving the pull-up signal and a first clock signal, and outputting a first output signal from a first output signal terminal according to the pull-up signal and the first clock signal; a second output sub-circuit for receiving the pull-up signal and a second clock signal, and outputting a second output signal from a second output signal terminal according to the pull-up signal and the second clock signal; a storage sub-circuit for storing the pull-up signal.