Patents by Inventor Qiuyang Wu
Qiuyang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11922106Abstract: A method includes extracting information associated with constraints and clock information from a file of a circuit design; determining a topological cone based on the extracted information for a partition of two or more partitions of the circuit design, and performing timing analysis on the partition of the two or more partitions based on the topological cone. The topological cone includes objects associated with the partition of the two or more partitions of the circuit design.Type: GrantFiled: July 23, 2021Date of Patent: March 5, 2024Assignee: SYNOPSYS, INC.Inventors: Abhishek Nandi, Qiuyang Wu, Yogesh Dilip Save
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Publication number: 20230201136Abstract: Provided herein are methods of managing, preventing, or treating a neuronal disorder in a subject, such as Alzheimer's disease, comprising monitoring the expression level of phosphoglycerate dehydrogenase (PHGDH) in the subject over an observation period of time, and administering to the subject an effective amount of a therapy for managing, preventing or treating the neuronal disorder.Type: ApplicationFiled: February 26, 2021Publication date: June 29, 2023Inventors: Zixu ZHOU, Qiuyang WU, Sheng ZHONG, Zhangming YAN
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Publication number: 20220027542Abstract: A method includes extracting information associated with constraints and clock information from a file of a circuit design; determining a topological cone based on the extracted information for a partition of two or more partitions of the circuit design, and performing timing analysis on the partition of the two or more partitions based on the topological cone. The topological cone includes objects associated with the partition of the two or more partitions of the circuit design.Type: ApplicationFiled: July 23, 2021Publication date: January 27, 2022Inventors: Abhishek NANDI, Qiuyang WU, Yogesh Dilip SAVE
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Patent number: 10423742Abstract: A method and apparatus for on chip variation path-based pessimism reduction and improving analysis of a hierarchical integrated circuit design in an electrical circuit. The circuit has one or more block circuit levels and a top circuit level. The method in one embodiment comprises characterizing the top circuit level to produce a context function, the context function used by the block circuit level for evaluation.Type: GrantFiled: January 24, 2017Date of Patent: September 24, 2019Assignee: Synopsys, Inc.Inventors: Qiuyang Wu, Martin Ranke, Min Li
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Publication number: 20180210986Abstract: A method and apparatus for on chip variation path-based pessimism reduction and improving analysis of a hierarchical integrated circuit design in an electrical circuit. The circuit has one or more block circuit levels and a top circuit level. The method in one embodiment comprises characterizing the top circuit level to produce a context function, the context function used by the block circuit level for evaluation.Type: ApplicationFiled: January 24, 2017Publication date: July 26, 2018Inventors: Qiuyang Wu, Martin Ranke, Min Li
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Patent number: 9754069Abstract: Embodiments perform static timing analysis using a digital representation of a circuit. The digital representation of the circuit includes multiple instances of a cell in a hierarchical cell block circuit. Timing context information is determined for each instance of the cell included in the circuit. A merged timing context information is determined to bound and cover each of the plurality of instances of the cell. A slack estimate is determined for a pair of ports for each instance of the cell. The instance with the smallest slack estimate is identified. A slack estimate for a pair of ports of the cell is determined based on the merged timing information of the cell. A timing credit is determined for the pair of ports based on the slack of the instance with the smallest slack and the slack estimate from the bound information for the pair of ports.Type: GrantFiled: October 16, 2015Date of Patent: September 5, 2017Assignee: Synopsys, Inc.Inventors: Qiuyang Wu, Chang Zhao
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Publication number: 20170109468Abstract: Embodiments perform static timing analysis using a digital representation of a circuit. The digital representation of the circuit includes multiple instances of a cell in a hierarchical cell block circuit. Timing context information is determined for each instance of the cell included in the circuit. A merged timing context information is determined to bound and cover each of the plurality of instances of the cell. A slack estimate is determined for a pair of ports for each instance of the cell. The instance with the smallest slack estimate is identified. A slack estimate for a pair of ports of the cell is determined based on the merged timing information of the cell. A timing credit is determined for the pair of ports based on the slack of the instance with the smallest slack and the slack estimate from the bound information for the pair of ports.Type: ApplicationFiled: October 16, 2015Publication date: April 20, 2017Inventors: Qiuyang Wu, Chang Zhao
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Patent number: 8701075Abstract: A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block.Type: GrantFiled: April 8, 2013Date of Patent: April 15, 2014Assignee: Synopsys, Inc.Inventors: Florentin Dartu, Patrick D. Fortner, Kayhan Kucukcakar, Qiuyang Wu
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Patent number: 8473886Abstract: A static timing analysis (STA) technique including a main process and a parallel process is described. In the main process, an IC design can be loaded and then linked to a cell library. Timing constraints to be applied to the IC design can be loaded. A timing update for the IC design can be performed. A report based on the timing update can be output. In the parallel process, the interconnect parasitics can be back-annotated onto the IC design. In one embodiment, the interconnect parasitics can be processed and stored on disk. Information on attaching to the stored parasitic data can be generated and provided to the main process during the step of performing the timing update. The parallel process can run concurrently and asynchronously with the main process.Type: GrantFiled: September 10, 2010Date of Patent: June 25, 2013Assignee: Synopsys, Inc.Inventors: Subramanyam Sripada, Qiuyang Wu, Patrick D. Fortner
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Patent number: 8443328Abstract: A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block.Type: GrantFiled: June 14, 2010Date of Patent: May 14, 2013Assignee: Synopsys, Inc.Inventors: Florentin Dartu, Patrick D. Fortner, Kayhan Kucukcakar, Qiuyang Wu
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Patent number: 8261220Abstract: Partitioning of a design allows static timing analysis (STA), signal integrity, and noise analysis to be performed in parallel on multiple, less demanding, and more available hardware resources. Therefore, runtime and throughput of the analysis can be significantly shortened. Notably, the partitioning can include redundancy. That is, partitions are allowed to share objects in order to preserve the timing path completeness and design structural integrity. Due to this redundancy, these partitions can account for many constraints specifically imposed by STA and ensure minimal inter-partition data dependency during the analysis. Once these partitions are populated, analysis can be performed on those partitions in parallel to generate the same timing results as if the design had been analyzed flat as a single unit. Therefore, the performance of the analysis can be optimized without compromising the accuracy and quality of results.Type: GrantFiled: November 30, 2009Date of Patent: September 4, 2012Assignee: Synopsys, Inc.Inventors: Qiuyang Wu, Brian Clerkin
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Publication number: 20120066656Abstract: A static timing analysis (STA) technique including a main process and a parallel process is described. In the main process, an IC design can be loaded and then linked to a cell library. Timing constraints to be applied to the IC design can be loaded. A timing update for the IC design can be performed. A report based on the timing update can be output. In the parallel process, the interconnect parasitics can be back-annotated onto the IC design. In one embodiment, the interconnect parasitics can be processed and stored on disk. Information on attaching to the stored parasitic data can be generated and provided to the main process during the step of performing the timing update. The parallel process can run concurrently and asynchronously with the main process.Type: ApplicationFiled: September 10, 2010Publication date: March 15, 2012Applicant: Synopsys, Inc.Inventors: Subramanyam Sripada, Qiuyang Wu, Patrick D. Fortner
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Publication number: 20110307850Abstract: A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block.Type: ApplicationFiled: June 14, 2010Publication date: December 15, 2011Applicant: SYNOPSYS, INC.Inventors: Florentin Dartu, Patrick D. Fortner, Kayhan Kucukcakar, Qiuyang Wu
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Publication number: 20110131540Abstract: Partitioning of a design allows STA to be performed in parallel on multiple, less demanding, and more available hardware resources. Therefore, runtime of STA can be significantly shortened. Notably, the partitioning can include redundancy. That is, partitions are allowed to share objects in order to preserve the timing path completeness and design structural integrity. Due to this redundancy, these partitions can account for many constraints specifically imposed by STA. Once these partitions are populated, analysis can be performed on those partitions in parallel to generate the same timing results as if the design had been analyzed flat as a single unit. Therefore, the performance of STA can be optimized without compromising the accuracy and quality of results.Type: ApplicationFiled: November 30, 2009Publication date: June 2, 2011Applicant: Synopsys, Inc.Inventors: Qiuyang Wu, Brian Clerkin
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Patent number: 7739098Abstract: Static timing analysis attempts to exhaustively analyze all critical paths of a design. With ever decreasing geometries and ever increasing design complexity, manually identifying timing violations with standard static timing analysis can be very complex and time consuming. A static timing analysis tool can advantageously manage multiple runs having different modes and corners and automatically merge the results generated by the runs. The STA tool can perform the runs either in parallel or in series. Advantageously, the STA tool can save the full timing analysis generated by each run and then extract information from these saved results to form merged results for the design. These merged results can provide different levels of analysis coverage, supply path information at various levels of detail, allow selectable accessibility to information, and highlight propagation of timing changes/violations in the design.Type: GrantFiled: February 4, 2004Date of Patent: June 15, 2010Assignee: Synopsys, Inc.Inventors: Kayhan Küçükçakar, Steve Hollands, Brian Clerkin, Loa Mize, Qiuyang Wu, Subramanyam Sripada, Andrew J. Seigel
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Publication number: 20050172250Abstract: Static timing analysis attempts to exhaustively analyze all critical paths of a design. With ever decreasing geometries and ever increasing design complexity, manually identifying timing violations with standard static timing analysis can be very complex and time consuming. A static timing analysis tool can advantageously manage multiple runs having different modes and corners and automatically merge the results generated by the runs. The STA tool can perform the runs either in parallel or in series. Advantageously, the STA tool can save the full timing analysis generated by each run and then extract information from these saved results to form merged results for the design. These merged results can provide different levels of analysis coverage, supply path information at various levels of detail, allow selectable accessibility to information, and highlight propagation of timing changes/violations in the design.Type: ApplicationFiled: February 4, 2004Publication date: August 4, 2005Applicant: Synopsys, Inc.Inventors: Kayhan Kucukcakar, Steve Hollands, Brian Clerkin, Loa Mize, Qiuyang Wu, Subramanyam Sripada, Andrew Seigel