Abstract: The disclosure relates to the field of electronic materials, and in particular to a composite film of fluorinated polybenzoxazole (6FPBO) and triple-shelled mesoporous silica hollow spheres, and to its preparation and use. The composite film comprises fluorinated polybenzoxazole as a matrix and amino-functionalized triple-shelled mesoporous silica hollow spheres which are dispersed in the fluorinated polybenzoxazole matrix. A mass ratio of (amino-functionalized triple-shelled mesoporous silica hollow spheres)/(fluorinated polybenzoxazole) is 1/100 to 5/100. The composite film has excellent thermal stability and a lower dielectric constant.

Abstract: A battery module includes a battery column, a heat insulation pad and a side plate. The battery column includes a plurality of batteries, and the batteries are arranged in a first direction. The heat insulation pad is disposed between two adjacent batteries in the battery column. The side plate is disposed on a side surface of the battery column and extends in the first direction. At least one heat-resistant region is disposed on the side plate and corresponds to a position of the heat insulation pad. The heat-resistant region is any one of a through hole, a blind hole, and a notch or a combination of two or more of the foregoing communicated with each other. At least a portion of an orthographic projection of the heat insulation pad on the side plate is disposed within the heat-resistant region.

Abstract: Disclosed are an AlGaN/GaN heterojunction HEMT device compatible with a Si-CMOS process and a manufacturing method therefor. The device comprises: an AlGaN/GaN heterojunction epitaxial layer, a passivation layer, a gate dielectric layer, a gold-free gate electrode and gold-free source and drain electrodes. The AlGaN/GaN heterojunction epitaxial layer comprises a substrate, a nitride nucleating layer, a nitride buffer layer, a GaN channel layer, an AlGaN intrinsic barrier layer and an AlGaN heavily-doped layer from bottom to top in sequence; the AlGaN heavily-doped layer generates charges by an ionized donor so as to compensate for a surface acceptor level of a semiconductor, thus suppressing a current collapse; and ohmic contact with an electrode is formed by low-temperature annealing; and the gold-free electrode prevents Au from polluting a Si-CMOS process line.

Abstract: An enhancement-mode GaN-based HEMT device on Si substrate and a manufacturing method thereof. The device includes a Si substrate, an AlN nucleation layer, AlGaN transition layers, an AlGaN buffer layer, a low temperature AlN insertion layer, an AlGaN main buffer layer, an AlGaN/GaN superlattice layer, an GaN channel layer, and an AlGaN barrier layer. Both sides of a top end of the HEMT device are a source electrode and a drain electrode respectively, and a middle of the top end is a gate electrode. A middle of the AlGaN barrier layer is etched through to form a recess, and a bottom of the recess is connected to the GaN channel layer. A passivation protective layer and a gate dielectric layer are deposited on the bottom of the recess, and the gate electrode is located above the dielectric layer.

Abstract: An enhancement-mode GaN-based HEMT device on Si substrate and a manufacturing method thereof. The device includes a Si substrate, an AlN nucleation layer, AlGaN transition layers, an AlGaN buffer layer, a low temperature AlN insertion layer, an AlGaN main buffer layer, an AlGaN/GaN superlattice layer, an GaN channel layer), and an AlGaN barrier layer. Both sides of a top end of the HEMT device are a source electrode and a drain electrode respectively, and a middle of the top end is a gate electrode. A middle of the AlGaN barrier layer is etched through to form a recess, and a bottom of the recess is connected to the GaN channel layer. A passivation protective layer and a gate dielectric layer are deposited on the bottom of the recess, and the gate electrode is located above the dielectric layer.

Abstract: A method of testing an interconnect between an electronic component and an external memory comprises receiving a data word having data bits and translating the data word into multiple cycles. The multiple cycles are transmitted through the interconnect to the external memory one after another such that a value of the data bit being transmitted is switched for each cycle. In another embodiment, an electronic component comprises an interface, a translation unit, and a test module. The translation module is configured to receive a burst from the external memory through the interface and is configured to translate the burst into a data word. The test module is configured to receive the data word from the translation module and is configured to compare the data word to a test pattern to detect an interconnect defect.

Abstract: A method of testing an interconnect between an electronic component and an external memory comprises receiving a data word having data bits and translating the data word into multiple cycles. The multiple cycles are transmitted through the interconnect to the external memory one after another such that a value of the data bit being transmitted is switched for each cycle. In another embodiment, an electronic component comprises an interface, a translation unit, and a test module. The translation module is configured to receive a burst from the external memory through the interface and is configured to translate the burst into a data word. The test module is configured to receive the data word from the translation module and is configured to compare the data word to a test pattern to detect an interconnect defect.