Abstract: A method of fabricating semiconductor device includes forming a plurality of gates on a substrate, forming a top layer on a top surface of each gate, forming sidewall spacers on opposite sides of each gate, and forming sacrificial spacers on the sidewall spacers. The method further includes performing a dry etching process on the substrate using the top layer and the sacrificial spacers as a mask to form a recess of a first width in the substrate between two adjacent gates, performing an isotropic wet etching process on the recess to expand the first width to a second width, and performing an orientation selective wet etching process on the recess to shape the rectangular-shaped recess into a ?-shaped recess.

Abstract: Method of fabricating a semiconductor device includes forming a gate having a first material on a substrate and forming a layer of a second material overlaying the gate. Sidewall spacers are formed on opposite sides of the gate. The substrate is dry etched using the layer of second material and the sidewall spacers as a mask forming a recess in the substrate between two adjacent gates. A liner oxide layer is formed on inner walls of the recess. The liner oxide layer is removed by isotropic wet etching. Orientation selective wet etching is performed on the recess to shape the inner wall of the recess so as to cause the inner wall of the recess to be sigma-shaped. By removing the substrate portions having lattice defects due to dry etching through oxidation and wet etching, defect-free epitaxial growth performance is realized.

Abstract: This invention discloses a reaction apparatus for wafer treatment, an electrostatic chuck and a wafer temperature control method, in the field of semiconductor processing. The electrostatic chuck comprises an insulating layer for supporting a wafer and a lamp array disposed in the insulating layer. Each lamp of the lamp array can be independently controlled to turn on and off and/or to adjust the output power. By controlling the on/off switch and/or output power of each lamp of the lamp array the temperature of the wafer held on the ESC is adjusted and temperature non-uniformity can be more favourably adjusted, greatly improving wafer temperature uniformity, particularly alleviating non-radial temperature non-uniformity.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a gate having a first material on a substrate and a layer of a second material overlaying the gate. Sidewall spacers are formed on opposite sides of the gate. A characteristic of a portion of the substrate between adjacent sidewall spacers is changed using the layer of second material and the sidewall spacers as a mask. An isotropic wet etch process is performed to remove the substrate portion with a changed characteristic to form a recess in the substrate. An orientation selective wet etching process is performed on the recess to shape the inner walls of the recess into sigma-shape. Changing a substrate characteristic in conjunction with isotropic wet etching prevents the substrate from being damaged, and therefore can obtain defect free epitaxial SiGe growth performance.

Abstract: A method of fabricating semiconductor device includes forming a plurality of gates on a substrate, forming a top layer on a top surface of each gate, forming sidewall spacers on opposite sides of each gate, and forming sacrificial spacers on the sidewall spacers. The method further includes performing a dry etching process on the substrate using the top layer and the sacrificial spacers as a mask to form a recess of a first width in the substrate between two adjacent gates, performing an isotropic wet etching process on the recess to expand the first width to a second width, and performing an orientation selective wet etching process on the recess to shape the rectangular-shaped recess into a ?-shaped recess.

Abstract: Method of fabricating a semiconductor device includes forming a gate having a first material on a substrate and forming a layer of a second material overlaying the gate. Sidewall spacers are formed on opposite sides of the gate. The substrate is dry etched using the layer of second material and the sidewall spacers as a mask forming a recess in the substrate between two adjacent gates. A liner oxide layer is formed on inner walls of the recess. The liner oxide layer is removed by isotropic wet etching. Orientation selective wet etching is performed on the recess to shape the inner wall of the recess so as to cause the inner wall of the recess to be sigma-shaped. By removing the substrate portions having lattice defects due to dry etching through oxidation and wet etching, defect-free epitaxial growth performance is realized.

Abstract: A semiconductor device and a manufacturing method thereof are disclosed. The method comprises: providing a substrate with a first dielectric layer and a gate, wherein the gate is embedded in the first dielectric layer and an upper portion of the gate is an exposed first metal; and covering only the exposed first metal with a conductive material that is harder to be oxidized than the first metal by a selective deposition. An advantage of the present invention is that the metal of the upper surface of the gate is prevented from being oxidized by covering the metal gate with the conductive material that is relatively harder to be oxidized, thereby facilitating the formation of an effective electrical connection to the gate.

Abstract: This disclosure relates to a method of forming a gate pattern and a semiconductor device. The gate pattern comprises a plurality of parallel gate bars, and each gate bar is broken up by gaps. The method comprises: making an etching characteristic of a gate material layer at least at positions where the gaps are to be formed different from that at remaining positions; forming a plurality of parallel openings in a second resist layer; performing a first etching process on the gate material layer with the second resist layer as a mask, wherein portions of the gate material layer at least at the positions where the gaps are to be formed are selectively left; and performing a second etching process on the gate material layer so as to selectively remove the portions. This method can more accurately control the shape and size of the gate pattern.

Abstract: This disclosure is directed to a method of forming a gate pattern and a semiconductor device. The method comprises: providing a plurality of stacked structures which are parallel to each other and extend continuously in a first direction, and which are composed of a gate material bar and an etching barrier bar thereon; leaving second resist regions between gaps to be formed adjacent to each other across gate bars by a second photolithography process; selectively removing the etching barrier bars by a second etching process; forming a third resist layer having a plurality of openings parallel to each other and extending continuously in a second direction substantially perpendicular to the first direction by a third photolithography process; and forming the gate pattern by a third etching process. The method is capable of having a larger photolithography process window and better controlling the shape and size of a gate pattern.

Abstract: A method for forming a metal gate includes providing a substrate, subsequently forming a dummy gate on the substrate, forming spacers on sidewalls of the dummy gate, forming a stop layer on the substrate, the dummy gate and spacers of the dummy gate, and forming a sacrificial dielectric layer on the dummy gate and the stop layer. The method further includes removing a part of the sacrificial dielectric layer and the stop layer until the dummy gate is exposed and, removing a residual sacrificial dielectric layer, depositing an interlayer dielectric layer on the dummy gate and the stop layer, polishing the interlayer dielectric layer until the dummy gate is exposed, removing the dummy gate to form a trench, and forming a metal gate in the trench. The interlayer dielectric layer is flat and substantially flush with the dummy gate, so that no recesses are formed thereon.