Abstract: In a receiver a method for extracting first and second signals from a single signal includes receiving the single signal, generating a recovered first signal by extracting and phase locking the first signal with respect to the phase of a local clock, decoding over a decode frame time the data representing an encoded phase difference at the start of the decode frame time, generating a phase difference between the first signal and the second signal as a function of data representing phase difference from a current decode frame time and data representing an encoded phase difference from an immediately prior decode frame time, subtracting the generated phase difference from the phase of the recovered first signal, and generating a recovered second signal by phase locking a signal at the second frequency at the recovered second phase.

Abstract: A frequency synthesizer includes a hardware digital controlled oscillator (HDCO) running at a first clock rate fS for generating an output clock signal in response to a control input, and a digital phase locked loop (DPLL) responsive to a reference input sampled at a second clock rate fsamp, the first clock rate fS being N times greater than the second clock rate fsamp, The DPLL includes a loop filter and a software digital controlled oscillator (SDCO). A first, first order linear interpolation anti-imaging filter running at a clock rate higher than said second clock rate fsamp is coupled to an output of the loop filter for providing the control input to the HDCO. A second, first order linear interpolation anti-imaging filter running at said second clock rate coupled to the output of said loop filter to provide an input to said SDCO.

Abstract: A frequency synthesizer includes a hardware digital controlled oscillator (HDCO) running at a first clock rate fS for generating an output clock signal in response to a control input, and a digital phase locked loop (DPLL) responsive to a reference input sampled at a second clock rate fsamp, the first clock rate fS being N times greater than the second clock rate fsamp, The DPLL includes a loop filter and a software digital controlled oscillator (SDCO). A first, first order linear interpolation anti-imaging filter running at a clock rate higher than said second clock rate fsamp is coupled to an output of the loop filter for providing the control input to the HDCO. A second, first order linear interpolation anti-imaging filter running at said second clock rate coupled to the output of said loop filter to provide an input to said SDCO.

Abstract: A clock synthesizer for synthesizing an output clock locked to a selected reference clock input has a pair of phase locked loops locked to respective reference clock inputs first generating first and second frequencies. One of the frequencies is selected to control a controlled oscillator for generating an output clock. The frequency offset between the first and second frequencies at the time of switching is stored and added to the frequency controlling the controlled oscillator.

Abstract: A compensation circuit for an oven-controlled crystal oscillator serving as a reference for a phase-locked loop in holdover mode is disclosed. A non-linear function module generates a modified aging signal that is a non-linear function of an aging signal. A first Kalman filter generates an estimate of the frequency drift of the crystal oscillator based on the temperature signal. A second Kalman filter generates an estimate of the frequency drift based on the modified aging signal. A combining and comparing module combines the estimates generated by the first and second Kalman filters and compares the estimates with detected frequency drift to produce an error signal to update the Kalman filters. In holdover mode the Kalman filters generate an error signal to correct the oscillator frequency based on updates obtained during operation of the phase-locked loop in normal mode.

Abstract: A clock synthesizer for synthesizing an output clock locked to a selected reference clock input has a pair of phase locked loops locked to respective reference clock inputs first generating first and second frequencies. One of the frequencies is selected to control a controlled oscillator for generating an output clock. The frequency offset between the first and second frequencies at the time of switching is stored and added to the frequency controlling the controlled oscillator.

Abstract: A method of compensating for integral nonlinear interpolation (INL) distortion in a clock synthesizer driven by a system clock running at a frequency fsys, involves introducing a selected nominal analog delay I*dt with an actual delay of I*dt+? at the output of the a first path with a digital controlled oscillator (DCO) and a digital-to-time converter (DTC) and a nominal digital delay I*D with an actual delay of I*D+? at the input of a second path with a DCO and a DTC that offsets the actual analog delay in the first path, adjusting the contents x(k) of a compensation module in the second path to align the output pulses of the first and second paths for different values of k, where k represents an interpolation point, iteratively repeating the two preceding steps for all N values of I, and averaging the contents x(k) of the compensation module to derive the compensation values to be applied to a one of the DTCs to correct for INL distortion.

Abstract: To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations.

Abstract: A method of compensating for integral nonlinear interpolation (INL) distortion in a clock synthesizer driven by a system clock running at a frequency fsys, involves introducing a selected nominal analog delay I*dt with an actual delay of I*dt+? at the output of the a first path with a digital controlled oscillator (DCO) and a digital-to-time converter (DTC) and a nominal digital delay I*D with an actual delay of I*D+? at the input of a second path with a DCO and a DTC that offsets the actual analog delay in the first path, adjusting the contents x(k) of a compensation module in the second path to align the output pulses of the first and second paths for different values of k, where k represents an interpolation point, iteratively repeating the two preceding steps for all N values of I, and averaging the contents x(k) of the compensation module to derive the compensation values to be applied to a one of the DTCs to correct for INL distortion.

Abstract: To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations.

Abstract: A precision frequency monitor provides a precision frequency monitor value (PFM) indicative of the precision of the frequency or period of an input reference signal. A first averaging module is responsive to the input reference signal to find an average frequency or period during successive predetermined time periods defining operational cycles. A second averaging module is responsive to an output of the first averaging module to average the output of the first averaging module over N operational cycles, where N is an integer, and output an updated PFM value every N operational cycles. An infinite impulse response (IIR) filter is responsive to the output of the first averaging module to filter the output of the first averaging module to output interim updated PFM values within each sequence of N operational cycles.

Abstract: In a digital phase locked loop comprising a PLL loop including a first software-implemented controlled oscillator (SDCO) responsive to a control value to generate output phase and frequency values locked to a reference input signal, and a hardware-implemented controlled oscillator responsive to output phase and frequency values from said first SDCO to synthesize said clock signals, hardware delays are compensated for by sampling said synthesized clock signals, or derivatives thereof, to generate synthesized clock phase values. The synthesized clock signal phase values are compared with feedback phase values derived from the PLL loop to generate a compensation value to modify the synthesized clock signals or derivatives thereof.

Abstract: A multi-channel phase locked loop (PLL) device has a plurality of PLL channels. Each channel includes a digitally controlled oscillator (DCO) supplying an output clock, via an output divider, to a respective output pin. A first multiplexer selects any of the PLL channels for alignment. A feedback calibration PLL is responsive to a feedback signal derived from an output clock of a selected channel at the respective output pin. A delay control module is responsive to an output of the feedback calibration PLL to adjust the phase of the output clock.

Abstract: A multi-channel phase locked loop (PLL) device has a plurality of PLL channels. Each channel includes a digitally controlled oscillator (DCO) supplying an output clock, via an output divider, to a respective output pin. A first multiplexer selects any of the PLL channels for alignment. A feedback calibration PLL is responsive to a feedback signal derived from an output clock of a selected channel at the respective output pin. A delay control module is responsive to an output of the feedback calibration PLL to adjust the phase of the output clock.

Abstract: In a digital phase locked loop comprising a PLL loop including a first software-implemented controlled oscillator (SDCO) responsive to a control value to generate output phase and frequency values locked to a reference input signal, and a hardware-implemented controlled oscillator responsive to output phase and frequency values from said first SDCO to synthesize said clock signals, hardware delays are compensated for by sampling said synthesized clock signals, or derivatives thereof, to generate synthesized clock phase values. The synthesized clock signal phase values are compared with feedback phase values derived from the PLL loop to generate a compensation value to modify the synthesized clock signals or derivatives thereof.

Abstract: A multi-loop phase locked loop (PLL) system with noise attenuation has a first PLL including a local oscillator, a second PLL coupled to an output of the first PLL, and a third PLL in a feedback path between the second PLL and first PLL. A first phase comparator compares an input signal with the first feedback signal to generate a first phase error signal for the first PLL. The first phase error signal is multiplied by a scaling factor k determining the amount of noise attenuation. The third PLL has a bandwidth preferably at least ten times higher than the second PLL so that the overall transfer function of the second and third PLLs is approximately the transfer function of the second PLL. The transfer function of the third PLL is multiplied by a scaling factor 1/k. This arrangement allows the use of an uncompensated local oscillator in the first PLL. The noise generated in the uncompensated local oscillator is reduced by the attenuation factor k.

Abstract: A precision frequency monitor provides a precision frequency monitor value (PFM) indicative of the precision of the frequency or period of an input reference signal. A first averaging module is responsive to the input reference signal to find an average frequency or period during successive predetermined time periods defining operational cycles. A second averaging module is responsive to an output of the first averaging module to average the output of the first averaging module over N operational cycles, where N is an integer, and output an updated PFM value every N operational cycles. An infinite impulse response (IIR) filter is responsive to the output of the first averaging module to filter the output of the first averaging module to output interim updated PFM values within each sequence of N operational cycles.

Abstract: A multi-loop phase locked loop (PLL) system with noise attenuation has a first PLL including a local oscillator, a second PLL coupled to an output of the first PLL, and a third PLL in a feedback path between the second PLL and first PLL. A first phase comparator compares an input signal with the first feedback signal to generate a first phase error signal for the first PLL. The first phase error signal is multiplied by a scaling factor k determining the amount of noise attenuation. The third PLL has a bandwidth preferably at least ten times higher than the second PLL so that the overall transfer function of the second and third PLLs is approximately the transfer function of the second PLL. The transfer function of the third PLL is multiplied by a scaling factor 1/k. This arrangement allows the use of an uncompensated local oscillator in the first PLL. The noise generated in the uncompensated local oscillator is reduced by the attenuation factor k.

Abstract: A digital infinite impulse response filter has a plurality of cascaded filter elements, with each filter element defining a pole of the filter and wherein the poles lie inside a unit circle. The filter elements are configured such that the p of the last filter element is a real number. In one embodiment the poles are arranged as complex conjugate pairs. In another embodiment the real part of the output of each filter element is extracted before being passed to the next filter element. This architecture offers improved idle tone with reduced complexity.

Abstract: A digital phase locked loop has a digital controlled oscillator, a phase comparator comparing the output signal of the digital controlled oscillator, or a signal derived therefrom, with a reference signal to produce a phase error signal. A loop filter produces a control signal for the digital controlled oscillator from an output of the phase comparator the loop filter. The loop filter has a proportional part producing a proportional component of the control signal, an integral part producing an integral component of the control signal, and an adder receiving the respective proportional and integral components at first and second inputs thereof to produce the control signal. The integral part includes a delayed feedback loop normally configured to accept the integral component at an input thereof. A first switch replaces the integral component at the input of the delayed feedback loop by the control signal in response to an activation signal.