Patents by Inventor Qu LUO

Qu LUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11980024
    Abstract: The present disclosure relates to the field of semiconductor technologies, and provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a semiconductor base, bit lines and word lines, wherein a plurality of active regions is provided in the semiconductor base; the bit lines are disposed in the semiconductor base, extend in a first direction and are connected to the active regions; and the word lines are disposed on the semiconductor base above the bit lines, extend in a second direction, and intersect with the active regions.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: May 7, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Qu Luo
  • Patent number: 11871555
    Abstract: A semiconductor structure and method for forming the semiconductor structure are provided. The method includes: providing a semiconductor substrate, which has a plurality of independent active areas that are isolated from each other by shallow trench isolation areas; forming trenches by etching the active areas and the shallow trench isolation areas, the trenches include first trenches and second trenches, the first trenches are located in the active areas, the second trenches are located in the shallow trench isolation areas, and the first trenches have a width greater than a width of the second trenches; forming word lines in the trenches, the word lines include first word lines and second word lines, each first word line is located in the respective first trench, each second word line is located in the respective second trench, and the first word lines have a width greater than a width of the second word lines.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Qu Luo, WenHao Hsieh
  • Patent number: 11862723
    Abstract: A manufacturing method of an integrated circuit memory includes: a substrate is provided; a bit line extending along a first direction is formed on the substrate; a word line extending along a second direction is formed on the bit line; and a vertical storage transistor is formed in an overlapping region where the word line and the bit line are spatially intersected, the vertical storage transistor being located on the bit line, and connected to the bit line.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Qu Luo
  • Publication number: 20220399345
    Abstract: The present disclosure relates to the field of semiconductor technologies, and provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a semiconductor base, bit lines and word lines, wherein a plurality of active regions is provided in the semiconductor base; the bit lines are disposed in the semiconductor base, extend in a first direction and are connected to the active regions; and the word lines are disposed on the semiconductor base above the bit lines, extend in a second direction, and intersect with the active regions.
    Type: Application
    Filed: June 9, 2021
    Publication date: December 15, 2022
    Inventor: Qu LUO
  • Publication number: 20220077289
    Abstract: Disclosed are a semiconductor device and a manufacturing method thereof. The method includes: providing a semiconductor substrate; forming a first wordline trench structure; forming a first sacrificial layer at the bottom of the first wordline trench structure; filling the first wordline trench structure located in active regions by epitaxial growth; forming a first insulation layer covering the top of the semiconductor substrate and the first wordline trench structure; forming a second wordline trench structure and a fin-type structure in the active regions, a depth of the second wordline trench structure being less than that of the first wordline trench structure, and a projection of the second wordline trench structure in a vertical direction completely overlapping with a projection of the first sacrificial layer in the vertical direction; removing the first sacrificial layer; and filling the first wordline trench structure, the second wordline trench structure and the wordline tunnel.
    Type: Application
    Filed: November 19, 2021
    Publication date: March 10, 2022
    Inventors: Qu Luo, Cheng Yeh Hsu
  • Publication number: 20220059694
    Abstract: A manufacturing method of an integrated circuit memory includes: a substrate is provided; a bit line extending along a first direction is formed on the substrate; a word line extending along a second direction is formed on the bit line; and a vertical storage transistor is formed in an overlapping region where the word line and the bit line are spatially intersected, the vertical storage transistor being located on the bit line, and connected to the bit line.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 24, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Qu LUO
  • Publication number: 20210358920
    Abstract: A semiconductor structure and method for forming the semiconductor structure are provided. The method includes: providing a semiconductor substrate, which has a plurality of independent active areas that are isolated from each other by shallow trench isolation areas; forming trenches by etching the active areas and the shallow trench isolation areas, the trenches include first trenches and second trenches, the first trenches are located in the active areas, the second trenches are located in the shallow trench isolation areas, and the first trenches have a width greater than a width of the second trenches; forming word lines in the trenches, the word lines include first word lines and second word lines, each first word line is located in the respective first trench, each second word line is located in the respective second trench, and the first word lines have a width greater than a width of the second word lines.
    Type: Application
    Filed: July 27, 2021
    Publication date: November 18, 2021
    Inventors: Qu Luo, WenHao Hsieh
  • Publication number: 20210351189
    Abstract: A memory and a method for forming the same are provided. In the method, a word line trench is formed in active regions and an isolation layer. The formed word line trench includes a first partial word line trench located in the active regions and a second partial word line trench located in the isolation layer. The width and depth of the second partial word line trench are greater than the width and depth of the first partial word line trench respectively. Therefore, when a word line structure is formed in the word line trench, the formed word line structure also includes a first partial word line structure located in the first partial word line trench and a second partial word line structure located in the second partial word line trench.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 11, 2021
    Inventors: Qu LUO, WenHao HSIEH