Patents by Inventor Quan A. Tran

Quan A. Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11715928
    Abstract: An integrated circuit assembly includes a support (e.g., package substrate or circuit board) and a semiconductor die including a device. The semiconductor die is mounted to the support with the device facing the support. The device can be, for example, a quantum well laser device or a photonics device. A layer of decoupling material is on the device. An underfill material is between the semiconductor die and the support, where the decoupling material is between the device and the underfill material. The decoupling layer decouples stress from transferring from the underfill material into the device. For example, the decoupling material forms only weak bonds with the underfill material and/or a passivation layer on the device, in an embodiment. Weak bonds include non-covalent bonds and non-ionic bonds, for example. The decoupling material can be, for instance, a PTFE film, a poly(p-xylylene) film, a fluorocarbon, or a compound lacking free hydroxyl groups.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: August 1, 2023
    Assignee: Intel Corporation
    Inventors: Priyanka Dobriyal, Susheel G. Jadhav, Ankur Agrawal, Quan A. Tran, Raiyomand F. Aspandiar, Kenneth M. Brown
  • Publication number: 20210066882
    Abstract: An integrated circuit assembly includes a support (e.g., package substrate or circuit board) and a semiconductor die including a device. The semiconductor die is mounted to the support with the device facing the support. The device can be, for example, a quantum well laser device or a photonics device. A layer of decoupling material is on the device. An underfill material is between the semiconductor die and the support, where the decoupling material is between the device and the underfill material. The decoupling layer decouples stress from transferring from the underfill material into the device. For example, the decoupling material forms only weak bonds with the underfill material and/or a passivation layer on the device, in an embodiment. Weak bonds include non-covalent bonds and non-ionic bonds, for example. The decoupling material can be, for instance, a PTFE film, a poly(p-xylylene) film, a fluorocarbon, or a compound lacking free hydroxyl groups.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 4, 2021
    Applicant: INTEL CORPORATION
    Inventors: Priyanka Dobriyal, Susheel G. Jadhav, Ankur Agrawal, Quan A. Tran, Raiyomand F. Aspandiar, Kenneth M. Brown
  • Patent number: 10070524
    Abstract: A glass core substrate for an integrated circuit (IC) device may be formed to include a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: September 4, 2018
    Assignee: Intel Corporation
    Inventors: Qing Ma, Quan A. Tran, Robert L. Sankman, Johanna M. Swan, Valluri R. Rao
  • Publication number: 20170288780
    Abstract: Apparatuses including integrated circuit (IC) optical assemblies and processes for fabrication of IC optical assemblies are disclosed herein. In some embodiments, the IC optical assemblies include an optical transmitter component electrically coupled to a first portion of a packaging substrate. The IC optical assemblies further include an optical transmitter driver component between the optical transmitter component and a second portion of the packaging substrate, wherein a first side of the optical transmitter driver component is electrically coupled to the optical transmitter component. The IC optical assemblies further include a plurality of bumps between a second side of the optical transmitter driver component and proximate the second portion of the packaging substrate, wherein the plurality of bumps are not directly coupled to the optical transmitter driver component.
    Type: Application
    Filed: March 31, 2016
    Publication date: October 5, 2017
    Inventors: Myung Jin Yim, Quan A. Tran, SeungJae Lee, Sandeep Razdan, Yigit O. Yilmaz, Pradeep Srinivasan, Jincheng Wang, Ansheng Liu
  • Patent number: 9686861
    Abstract: Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventors: Qing Ma, Quan A. Tran, Robert L. Sankman, Johanna M. Swan, Valluri R. Rao
  • Publication number: 20160284637
    Abstract: Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.
    Type: Application
    Filed: June 2, 2016
    Publication date: September 29, 2016
    Inventors: Qing Ma, Quan A. Tran, Robert L. Sankman, Johanna M. Swan, Valluri R. Rao
  • Publication number: 20120192413
    Abstract: Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.
    Type: Application
    Filed: April 9, 2012
    Publication date: August 2, 2012
    Inventors: Qing Ma, Quan A. Tran, Robert L. Sankman, Johanna M. Swan, Valluri R. Rao
  • Patent number: 8207453
    Abstract: Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: June 26, 2012
    Assignee: Intel Corporation
    Inventors: Qing Ma, Quan A. Tran, Robert L. Sankman, Johanna M. Swan, Valluri R. Rao
  • Publication number: 20110147055
    Abstract: Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.
    Type: Application
    Filed: December 17, 2009
    Publication date: June 23, 2011
    Inventors: Qing Ma, Quan A. Tran, Robert L. Sankman, Johanna M. Swan, Valluri R. Rao
  • Publication number: 20100085863
    Abstract: Provided herein are embodiments for adjusting a built-in bias of a media including a conductive layer and a ferroelectric layer above the conductive layer. In certain embodiments, a voltage signal is applied between the conductive layer of the media and an electrode (provided over at least a portion of the ferroelectric layer) to thereby tune the built-in bias so that the built-in bias moves in a direction of (i.e., towards) the desired built-in bias. In other embodiments, the temperature of the at least a portion of the ferroelectric layer of the media is elevated to thereby tune the built-in bias so that the built-in bias moves in a direction of (i.e., towards) the desired built-in bias. The desired built-in bias can be a zero built-in bias, or a non-zero built-in bias.
    Type: Application
    Filed: October 28, 2008
    Publication date: April 8, 2010
    Applicant: NANOCHIP, INC.
    Inventors: Nathan Franklin, Quan A. Tran, Qing Ma
  • Publication number: 20090213492
    Abstract: A memory device comprises a ferroelectric media comprising at least one ferroelectric film. The ferroelectric film has an as-grown spontaneous polarization of a first direction. A tip is position over the ferroelectric film and a first voltage is applied to the tip larger than a switching voltage of the ferroelectric film. One or both of the tip and the ferroelectric media is moved to form a first domain having a spontaneous polarization of opposite the first direction. The tip is then positioned over the first domain and a second voltage to the tip smaller than the first voltage to form a second domain smaller than the first domain and having a polarization of the first direction, the second domain defining the bit.
    Type: Application
    Filed: February 22, 2008
    Publication date: August 27, 2009
    Applicant: NANOCHIP, INC.
    Inventor: Quan A. Tran
  • Publication number: 20090129247
    Abstract: An information storage device comprises a ferroelectric media, write circuitry to provide a first signal and a second signal to the ferroelectric media, a tip platform and a cantilever operably associated with the tip platform. A tip extends from the cantilever toward the ferroelectric media and includes a first conductive material communicating the first signal from the write circuitry to the ferroelectric media and a second conductive material communicating the second signal from the write circuitry to the ferroelectric media. A insulating material arranged between the first conductive material and the second conductive material to electrically isolate the first conductive material from the second conductive material.
    Type: Application
    Filed: November 12, 2008
    Publication date: May 21, 2009
    Applicant: NANOCHIP, INC.
    Inventors: Quan A. Tran, Qing Ma, Donald Edward Adams, Nickolai Belov, Yevgeny Vasilievich Anoikin
  • Patent number: 7214995
    Abstract: According to one embodiment a microelectromechanical (MEMS) switch is disclosed. The MEMS switch includes a top movable electrode, and an actutaion electrode with an undoped polysilicon stopper region to contact the top movable electrode when an actuation current is applied. The undoped polysilicon stopper region prevents actuation charging that accumulates over time in a unipolar actuation condition.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: May 8, 2007
    Assignee: Intel Corporation
    Inventors: Tsung-Kuan Allen Chou, Quan A. Tran
  • Publication number: 20040017130
    Abstract: A material may be patterned and defined on the upper electrode of a film bulk acoustic resonator to provide a mass loading effect that adjusts the frequency of one film bulk acoustic resonator on a wafer relative to other resonators on the same wafer. The applied material that has a high degree of etch selectivity with respect to the material of the upper electrode of the film bulk acoustic resonator.
    Type: Application
    Filed: July 24, 2002
    Publication date: January 29, 2004
    Inventors: Li-Peng Wang, Qing Ma, Quan A. Tran, Teresa Rini, Michael Dibattista