Abstract: Various embodiments relate to optimization of an update package by performing analysis of matches. In some embodiments, a mechanism is provided to receive an updated executable file and a previous executable file. In addition, a mechanism is provided to determine a plurality of matches, each match representing a set of commands used to generate a portion of the updated executable file using the previous executable file. Furthermore, a mechanism is provided to analyze the matches and, based on the analysis, encode an optimized update package.

Abstract: A monitoring system and method of the power sequence signals are presented, so as to monitor a power sequence signals transmitted via the peripheral devices of a motherboard in operation process. The monitoring system includes a power supply unit and a Complex Programmable Logic Device (CPLD). The monitoring method includes activating the motherboard, and driving the CPLD to select any one of the peripheral devices in sequence being electrified; controlling, by the CPLD, operation powers of the peripheral devices through a General Purpose Input/Output (GPIO) pin, and recording the power sequence signals of the peripheral devices under different operation powers in a data register; and outputting, by the CPLD, the power sequence signals of the peripheral devices.

Abstract: A method for detecting a capacitor loss is applicable to detecting a plurality of by-pass capacitors connected in parallel to each other. The detection method includes the following steps, an alternating current (AC) signal is input into the by-pass capacitors, in which the AC signal has a plurality of test frequencies; test voltages of the by-pass capacitors at each of the test frequencies are recorded, so as to form a test result table; it is determined whether the test result table is the same as a standard voltage table; and when a result of the determination is NO, a fail signal is output. By applying the detection method, whether a loss exists in the by-pass capacitors can be effectively identified, thereby solving the problem that small capacitors are undetectable when large capacitors are connected in parallel to the small capacitors.

Abstract: A system and method for monitoring an input/output port status of peripheral devices are used for monitoring an operating status of each peripheral device of a main board. The system includes at least one peripheral device, a complex programmable logic device (CPLD), and an output apparatus. The CPLD is electrically connected to the peripheral devices. The CPLD further includes a protocol conversion unit and multiple data registers. The protocol conversion unit converts an operating status of the CPLD or the peripheral devices into device status information. The data register is used for storing the device status information. The output apparatus is electrically connected to the CPLD. The output apparatus is used for displaying the device status information in the data register. A user can observe the operating status of each of the peripheral devices of the main board conveniently.

Abstract: A device and a method for testing SAS channels which are applied to a plurality of pairs of SAS interfaces. The testing device includes a control terminal, a PCI-E microprocessor, a PCI-E-to-SAS adaptor, and a signal feedback module. The control terminal is used for selecting SAS channels and sending a control command; the PCI-E microprocessor is used for receiving the control command and sending a test signal to a PCI-E channel according to the control command; the PCI-E-to-SAS adaptor is used for converting a transmission signal between the PCI-E channel and the SAS channels; and the signal feedback module is used for connecting a first SAS interface to a second SAS interface in the SAS back plate. The PCI-E microprocessor compares whether the test signal sent to the first SAS channel is consistent with the test signal received from the second SAS interface.

Abstract: A device and a method for testing SAS channels which are applied to a plurality of pairs of SAS interfaces. The testing device includes a control terminal, a PCI-E microprocessor, a PCI-E-to-SAS adaptor, and a signal feedback module. The control terminal is used for selecting SAS channels and sending a control command; the PCI-E microprocessor is used for receiving the control command and sending a test signal to a PCI-E channel according to the control command; the PCI-E-to-SAS adaptor is used for converting a transmission signal between the PCI-E channel and the SAS channels; and the signal feedback module is used for connecting a first SAS interface to a second SAS interface in the SAS back plate. The PCI-E microprocessor compares whether the test signal sent to the first SAS channel is consistent with the test signal received from the second SAS interface.

Abstract: An accessory-testing device for an information processing apparatus includes a micro-processing unit (MPU) and a signal conversion unit. The MPU sends a mimic signal. The signal conversion unit is electrically connected to the MPU and an accessory respectively, for receiving the mimic signal and converting the mimic signal into a test signal to test the accessory. The accessory receives the test signal and then responds to the test signal to output a feedback signal. The feedback signal is received by the signal conversion unit and transmitted to the MPU, such that the MPU determines if the accessory operates normally according to the feedback signal. Conventional testing methods are Therefore, it is achieved that the effects of reducing the inspection time and improving the production efficiency.

Abstract: A system and method for parallel burning using multiplex technology is used for burning chips of different bus types on the same transmission bus at the same time in parallel. A main control unit divides bandwidth of the transmission bus into different frequency bands, sends a control command including a command for sending data carrying bus signals of designated types, and controls data carrying the bus signals of the designated types to be transmitted in designated frequency bands of the transmission bus. Then, a sending unit sends the data carrying the bus signals of the designated types in the designated frequency band. Finally, receiving units receive the data transmitted in the designated frequency bands, and then output them to a plurality of burners such as to burn the data onto the chips of the designated bus types in parallel.

Abstract: An in-system programming system and method is provided, which is applicable for chip programming of a computer motherboard. Firstly, a programming interface is configured in the computer motherboard, in which one end of the programming interface is connected to an on-board programmer, and the other end is connected to a plurality of chips to be programmed, thereby achieving the communication between the on-board programmer and the chips. Next, a motherboard connector and the programming interface are connected, and the motherboard connector and the on-board programmer are communicated through a communication interface of the on-board programmer. Then, the other end of the motherboard connector is connected to a programmable master-control program.