Abstract: An array substrate and a display device are provided. The array substrate includes a plurality of sub-pixel repeating units, each sub-pixel repeating unit includes four first color sub-pixels, two second color sub-pixels and two third color sub-pixels, in each sub-pixel repeating unit, the shape of each first color sub-pixel is an axisymmetric figure, centers of the four first color sub-pixels are located on a same virtual line, a center of one of the two second color sub-pixels and a center of one of the two third color sub-pixels are located on a first side of the virtual line, a center of the other one of the two second color sub-pixels and a center of the other one of the two third color sub-pixels are located on a second side of the virtual line.

Abstract: Techniques are described for designing and forming cells comprising transistor devices for an integrated circuit. In an example, an integrated circuit structure includes a plurality of cells arranged in rows where some rows have different cell heights compared to other rows. Additionally, the various rows of cells may contain semiconductor nanoribbons having different widths between different rows. For example, any number of first rows of cells can each have a first height and any number of second rows can each have a second height that is smaller than the first height. The first rows of cells may include transistors with semiconductor nanoribbons having a first width and the second rows of cells may include transistors with semiconductor nanoribbons having a second width smaller than the first width. In some cases, any of the first rows of cells may also include transistors with semiconductor nanoribbons having the second width.

Abstract: Techniques are described for designing and forming cells having transistor devices. In an example, an integrated circuit structure includes a plurality of cells where adjacent cells have a decreased distance between them along their height and a staggered via arrangement. Accordingly, a first cell may be adjacent to a second cell along a shared cell boundary. A first via is provided between a first gate structure of the first cell adjacent to the cell boundary and a first metal layer above the first gate structure, and a second via is provided between a second gate structure of the second cell adjacent to the cell boundary and a second metal layer above the second gate structure. No part of the first via is aligned with any part of the second via along the first direction.

Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes: a base substrate, a plurality of sub-pixels, a pixel defining layer, and a planarization layer. The pixel defining layer includes a main body portion, the main body portion includes a first main body sub-portion and a second main body sub-portion, the second main body sub-portion protrudes relative to the first main body sub-portion to form a separation structure, at least one of the plurality of film layers is broken at the separation structure, an orthographic projection of a part of the light-emitting functional layer in the opening on the base substrate at least partially overlaps with an orthographic projection of a part of the light-emitting functional layer located on a side of the main body portion away from the base substrate on the base substrate.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof, as well as a memory system. The semiconductor device includes a first semiconductor structure comprising a first well region and transistors in the first well region, and a second semiconductor structure bonded with the first semiconductor structure and including a second well region, and fin field effect transistors in the second well region. Each fin field effect transistor includes a fin structure, a gate oxide layer in contact with a top surface and side surfaces of the fin structure, and a gate layer covering the gate oxide layer.

Abstract: A display substrate and a display device. The display substrate includes a base substrate, a plurality of sub-pixels, and a partition structure. The plurality of sub-pixels are located on the base substrate; each sub-pixel includes a light-emitting element; the light-emitting element includes a light-emitting functional layer and a first electrode and a second electrode located on either side of the light-emitting functional layer; the second electrode is located between the light-emitting functional layer and the base substrate; and the light-emitting functional layer includes a charge generation layer. The partition structure is located on the base substrate and between adjacent sub-pixels; and the charge generation layer in the light-emitting functional layer is disconnected at the positions where the partition structure is located.

Abstract: The present disclosure provides a pixel array and a display device. The pixel array includes first sub-pixels, second sub-pixels and third sub-pixels; the first sub-pixels and the third sub-pixels are alternately arranged along a first direction to form first pixel groups, and are alternately arranged along a second direction to form third pixel groups; the second sub-pixels are arranged along the first direction to form second pixel groups, and are arranged along the second direction to form fourth pixel groups; wherein the first pixel groups and the second pixel groups are alternately arranged in the second direction; the third pixel groups and the fourth pixel groups are alternately arranged along the first direction; wherein a shape of the second sub-pixel includes a polygon, a plurality of sides of the polygon include straight lines or arcs, and the shape of the second sub-pixel includes at most one symmetry axis.

Abstract: The present disclosure provides a display substrate, which includes a base substrate (101), a first power supply line (321a), a plurality of first signal leads (341), a plurality of test connection traces (342), at least one first connection line (381), and a plurality of test signal access pins (361). At least one first signal lead (341) is electrically connected to at least one test signal access pin (361) through at least one test connection trace (342). The first connection line (381) is located at a side of the plurality of test connection traces (342) and the plurality of test signal access pins (361) close to an edge of the peripheral area in a first direction (X). The first connection line (381) at least extends along a second direction (Y) and is electrically connected to the first power supply line (321a).

Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.

Abstract: A display substrate includes a pixel defining layer, a plurality of light emitting devices, a first isolation portion, and a light adjustment layer. The pixel defining layer has a plurality of openings. A portion of a light emitting device is located in an opening. The light emitting device includes a first light-emitting layer and a cathode that are disposed sequentially. The first isolation portion is disposed on the pixel defining layer and located between two adjacent openings, and the first isolation portion separates first light-emitting layers and cathodes of light emitting devices located in the two adjacent openings. The light adjusting layer covers the pixel defining layer, the plurality of light emitting devices, and the first isolation portion. A refractive index of the light adjustment layer is different from that of the first isolation portion.

Abstract: The present disclosure provides a to-be-evaporated substrate, a display substrate and a method of manufacturing a display substrate. The to-be-evaporated substrate may include: a substrate including a to-be-evaporated region and a non-evaporated region, where the non-evaporated region surrounds the to-be-evaporated region; a support pattern, disposed on the substrate and located in the non-evaporated region, where the support pattern includes a plurality of supporters for supporting a mask and further includes a first symmetrical pattern formed by a plurality of supporters, and the plurality of supporters forming the first symmetrical pattern are arranged along a perimeter of the to-be-evaporated region. The present disclosure can improve evaporation effect.

Abstract: Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.

Abstract: A method of making a bio-based, slow recovery polyurethane foam includes preparing an aqueous mixture that includes a resin and an additive. The resin, the additive, or both, can be bio-based. The method can include combining a hydrophilic polyurethane prepolymer with the aqueous mixture. The method can include chemically reacting the hydrophilic polyurethane prepolymer with the aqueous mixture to create a foam mixture. Chemically reacting the hydrophilic polyurethane prepolymer with the aqueous mixture may generate a foaming agent that includes carbon dioxide.

Abstract: A display baseplate and a manufacturing method thereof, and a display device, relate to the technical field of displaying. The display baseplate includes an active area and a border area located on at least one side of the active area. The border area includes: a substrate; and a first conductive layer disposed on one side of the substrate; wherein at least one first opening is disposed on the first conductive layer, and the orthographic projection of the first conductive layer on the substrate does not overlap with an orthographic projection of the at least one first opening on the substrate.

Abstract: The drive backplane includes a pixel area and a control area outside the pixel area. The control area includes a circuit area and a bus area between the circuit area and the pixel area. The drive backplane includes a substrate and a circuit layer provided on a side of the substrate. The circuit layer includes a plurality of pixel circuits, a plurality of gate lines, a gate drive circuit, bus lines, and a plurality of gate connection lines.

Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.

Abstract: The present disclosure discloses a 2.8 ?m and 3.5 ?m dual-wavelength mid-infrared fiber laser, which employs “0.98 ?m+1.15 ?m” pumping scheme, uses a fiber combiner to combine two pump lights into the double cladding Er-doped fluoride fiber. The Er ions in the ground state are first promoted to 4I11/2 level by the 0.98 ?m pump light, realizing 2.8 ?m lasing based on 4I11/2?4I13/2 transition, and further promoted to 4F9/2 level by the 1.15 ?m pump light, generating 3.5 ?m lasing based on 4F9/2?4I9/2 transition; followed by the 3.5 ?m laser transition, the Er ions would rapidly decay to 4I11/2 level via non radiative transition, realizing the re-population of 4I11/2 level, effectively enlarge the population inversion of 2.8 ?m transition, suppressing the self-termination of 2.8 ?m lasing and achieving 2.8 ?m and 3.5 ?m dual-wavelength cascaded lasing output.

Abstract: A fluorinated, alkoxysilyl-functional polymer is provided, obtainable by a method comprising the steps of: a) reacting an OH-functional (per)fluoropolyether (PFPE) with a polyisocyanate A under urethane formation reaction conditions, to obtain an isocyanate-functional intermediate B, b) reacting intermediate B with a secondary, alkoxysilyl-functional monoamine C, to obtain the alkoxysilyl-functional polymer. The polymer can be used as an additive in preparation of a coating with easy-clean, anti-stain and anti-scratch properties, which can advantageously be used for coating various substrates in consumer electronics or automotive applications such as glass, metal, metal alloy, anodized substrates, plastics, composite etc.

Abstract: Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.

Abstract: A display panel includes a driving backplane, a plurality of light-emitting devices spaced apart at a side of the driving backplane a pixel definition layer located at a same side of the driving backplane as the light-emitting device and provided with a plurality of openings and a lens layer located at a side of the light-emitting device away from the driving backplane. The lens layer includes a separating lens and an intermediate lens, the separating lens is provided with a light-transmitting hole, and the intermediate lens is located within a range surrounded by the light-transmitting hole and is spaced apart from a sidewall of the light-transmitting hole. The display panel further includes a dielectric layer covering the lens layer and filling the light-transmitting hole, and a cover plate located at a side of the dielectric layer away from the driving backplane.