Patents by Inventor Quan T. Nguyen

Quan T. Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7161409
    Abstract: A voltage reference circuit receives an input voltage through a first port and a time varying input signal through a second port. The voltage reference circuit includes a switching circuit that is responsive to the first and the second ports and that generates an AC signal from the input voltage. The voltage reference circuit further includes a voltage multiplier circuit, coupled to the switching circuit that receives the AC signal and creates a DC signal with a selected voltage level. The voltage reference circuit further includes a voltage regulator, coupled to the voltage multiplier circuit that regulates the DC signal from the voltage multiplier circuit. A regulated output voltage is provided through an output port.
    Type: Grant
    Filed: July 26, 2004
    Date of Patent: January 9, 2007
    Inventors: Douglas A. Scratchley, Quan T. Nguyen, Ernest Graetz
  • Patent number: 7011531
    Abstract: A structure and method to establish an electrical connection between a tester and an electrical component. A flexible dielectric layer has a first side and a second side. A through via extends through the first side and the second side of the dielectric layer. A blind via is placed in a position that is offset from the through via and extends laterally in a first direction from a section of the first through via to a section of the flexible dielectric layer. The blind via extends in a second direction from the first side of the flexible dielectric layer to a section of the flexible dielectric layer that is between the first side and the second side of the dielectric layer. An electrically conductive member extends through the through via and extends into the blind via, thereby filling the through via and the blind via. The electrically conductive member has a first surface and a second surface.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: March 14, 2006
    Assignee: International Business Machines Corporation
    Inventors: Frank D. Egitto, Keith J. Miller, Manh-Quan T. Nguyen
  • Patent number: 6955849
    Abstract: A method for producing small pitch z-axis electrical interconnections in layers of dielectric materials which are applied to printed wiring boards and diverse electronic packages. A method for parallel fabrication of intermediate structures which are subsequently jointed to form a final structure. In addition there is provided a z-interconnected electrical structure, employing dielectric materials such as resin coated copper, employable in the manufacture of diverse type of electronic packages, including printed wiring boards (PWBs), substrates, multi-chip modules and the like.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: October 18, 2005
    Assignee: International Business Machines Corporation
    Inventors: Brian E. Curcio, Frank D. Egitto, Robert M. Japp, Thomas R. Miller, Manh-Quan T. Nguyen, Douglas O. Powell
  • Patent number: 6881072
    Abstract: A structure and method to establish an electrical connection between a tester and an electrical component. A flexible dielectric layer has a first side and a second side. A through via extends through the first side and the second side of the dielectric layer. A blind via is placed in a position that is offset from the through via and extends laterally in a first direction from a section of the first through via to a section of the flexible dielectric layer. The blind via extends in a second direction from the first side of the flexible dielectric layer to a section of the flexible dielectric layer that is between the first side and the second side of the dielectric layer. An electrically conductive member extends through the through via and extends into the blind via, thereby filling the through via and the blind via. The electrically conductive member has a first surface and a second surface.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: April 19, 2005
    Assignee: International Business Machines Corporation
    Inventors: Frank D. Egitto, Keith J. Miller, Manh-Quan T. Nguyen
  • Patent number: 6790305
    Abstract: A method for producing small pitch z-axis electrical interconnections in layers of dielectric materials which are applied to printed wiring boards and diverse electronic packages. A method for parallel fabrication of intermediate structures which are subsequently jointed to form a final structure. In addition there is provided a z-interconnected electrical structure, employing dielectric materials such as resin coated copper, employable in the manufacture of diverse type of electronic packages, including printed wiring boards (PWBs), substrates, multi-chip modules and the like.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: September 14, 2004
    Assignee: International Business Machines Corporation
    Inventors: Brian E. Curcio, Frank D. Egitto, Robert M. Japp, Thomas R. Miller, Manh-Quan T. Nguyen, Douglas O. Powell
  • Publication number: 20040067347
    Abstract: A method for producing small pitch z-axis electrical interconnections in layers of dielectric materials which are applied to printed wiring boards and diverse electronic packages. A method for parallel fabrication of intermediate structures which are subsequently jointed to form a final structure. In addition there is provided a z-interconnected electrical structure, employing dielectric materials such as resin coated copper, employable in the manufacture of diverse type of electronic packages, including printed wiring boards (PWBs), substrates, multi-chip modules and the like.
    Type: Application
    Filed: October 8, 2002
    Publication date: April 8, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian E. Curcio, Frank D. Egitto, Robert M. Japp, Thomas R. Miller, Manh-Quan T. Nguyen, Douglas O. Powell
  • Publication number: 20040063352
    Abstract: A structure and method to establish an electrical connection between a tester and an electrical component. A flexible dielectric layer has a first side and a second side. A through via extends through the first side and the second side of the dielectric layer. A blind via is placed in a position that is offset from the through via and extends laterally in a first direction from a section of the first through via to a section of the flexible dielectric layer. The blind via extends in a second direction from the first side of the flexible dielectric layer to a section of the flexible dielectric layer that is between the first side and the second side of the dielectric layer. An electrically conductive member extends through the through via and extends into the blind via, thereby filling the through via and the blind via. The electrically conductive member has a first surface and a second surface.
    Type: Application
    Filed: October 1, 2002
    Publication date: April 1, 2004
    Applicant: International Business Machines Corporation
    Inventors: Frank D. Egitto, Keith J. Miller, Manh-Quan T. Nguyen
  • Patent number: 6518516
    Abstract: A multilayered laminate, substructures and associated methods of fabrication are presented. The multilayered laminate includes in sequential order: (a) a first intermediate layer having microvias and conductive lands; (b) a plurality of signal/power plane substructures, wherein a dielectric material of an intervening dielectric layer insulatively separates each pair of successive signal/power plane substructures and (c) a second intermediate layer having microvias and conductive lands.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: February 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Kim J. Blackwell, Frank D. Egitto, Voya R. Markovich, Manh-Quan T. Nguyen, Douglas O. Powell, David L. Thomas
  • Publication number: 20020108780
    Abstract: A multilayered laminate, substructures and associated methods of fabrication are presented. The multilayered laminate includes in sequential order: (a) a first intermediate layer having microvias and conductive lands; (b) a plurality of signal/power plane substructures, wherein a dielectric material of an intervening dielectric layer insulatively separates each pair of successive signal/power plane substructures and (c) a second intermediate layer having microvias and conductive lands.
    Type: Application
    Filed: April 11, 2002
    Publication date: August 15, 2002
    Applicant: International Business Machines Corporation
    Inventors: Kim J. Blackwell, Frank D. Egitto, Voya R. Markovich, Manh-Quan T. Nguyen, Douglas O. Powell, David L. Thomas