Abstract: Provided is a method for producing calcium zincate. The method comprises: an extraction step: mixing a ground zinc-containing raw material with an extracting agent, followed by filtration to obtain an extract, wherein the extracting agent is a mixed aqueous solution of ammonia and {NH4HCO3 and/or (NH4)2CO3; optionally, purifying the extract; a decarburization step: adding calcium oxide and/or calcium hydroxide to the extract, stirring, and filtering to obtain a first solid and a first filtrate; a calcium zincate synthesis step: adding calcium hydroxide and/or calcium oxide to the first filtrate, stirring to react, and filtering to obtain a second solid and a second filtrate; optionally, rinsing the second solid with water; a drying step: drying the second solid to obtain the final calcium zincate product.

Abstract: Provided is a method for producing calcium zincate. The method comprises: an extraction step: mixing a ground zinc-containing raw material with an extracting agent, followed by filtration to obtain an extract, wherein the extracting agent is a mixed aqueous solution of ammonia and {NH4HCO3 and/or (NH4)2CO3; optionally, purifying the extract; a decarburization step: adding calcium oxide and/or calcium hydroxide to the extract, stirring, and filtering to obtain a first solid and a first filtrate; a calcium zincate synthesis step: adding calcium hydroxide and/or calcium oxide to the first filtrate, stirring to react, and filtering to obtain a second solid and a second filtrate; optionally, rinsing the second solid with water; a drying step: drying the second solid to obtain the final calcium zincate product.

Abstract: A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors.

Abstract: A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors.

Abstract: A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors.

Abstract: A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors.