Abstract: A transmitter (100) includes a fractional N synthesizer, a baseband digital modulation stage coupled to the fractional N synthesizer in a first modulation mode, and a baseband I/Q modulation stage also coupled to the fractional N synthesizer and reusing the fractional N synthesizer in a second modulation mode. A method (300) of operating a transmitter includes transmitting a first signal from a transmitter using the fractional N synthesizer and the baseband digital modulation stage to modulate the first signal according to a first wireless protocol. The method (300) also includes transmitting a second signal from the transmitter using the baseband I/Q modulation stage and the fractional N synthesizer to modulate the second signal according to a second wireless protocol.

Abstract: A phase lock loop (100) includes a dual-state charge pump (120) having a first current source (220), a second current source (230) coupled in series to the first current source, a third current source (240), a fourth current source (250) coupled in series to the third current source, and control circuitry (210) coupled to the first, second, third, and fourth current sources. The charge pump can be programmed to be in an adapt mode with large up and down currents or in a normal mode with small up and down currents. The duration of the adapt mode can be programmed by a timer. The phase lock loop has a wide loop bandwidth and a faster lock time during the adapt mode and a narrow loop bandwidth and less phase noise during the normal mode.

Abstract: A level shifter for use in an integrated circuit that translates a binary input signal having a low voltage level to a binary output signal having a different voltage level. The level shifter (10) includes an input stage (20) that receives the input signal and provides control signals to a low state voltage translation circuit (30) and a high state voltage translation circuit (40). The low state voltage translation circuit (30) controls the level shifter (10) when the input signal is low and provides a bias signal to a bipolar device (Q2) adapted to pull the external output signal low. The high state voltage translation circuit (40) controls the level shifter (10) when the input signal is high and includes a voltage reducing circuit (44) operating as a current mirror with a pull-up PMOS transistor (P13) to couple an internal high voltage power supply to the output node (Vout).