Patents by Inventor Quang Le

Quang Le has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11908496
    Abstract: The present disclosure generally relate to spin-orbit torque (SOT) devices comprising a topological insulator (TI) modulation layer. The TI modulation layer comprises a plurality of bismuth or bismuth-rich composition modulation layers, a plurality of TI lamellae layers comprising BiSb having a (012) crystal orientation, and a plurality of texturing layers. The TI lamellae layers comprise dopants or clusters of atoms, the clusters of atoms comprising a carbide, a nitride, an oxide, or a composite ceramic material. The clusters of atoms are configured to have a grain boundary glass forming temperature of less than about 400° C. Doping the TI lamellae layers comprising BiSb having a (012) crystal orientation with clusters of atoms comprising a carbide, a nitride, an oxide, or a composite ceramic material enable the SOT MTJ device to operate at higher temperatures while inhibiting migration of Sb from the BiSb of the TI lamellae layers.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: February 20, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Quang Le, Brian R. York, Cherngye Hwang, Susumu Okamura, Xiaoyong Liu, Kuok San Ho, Hisashi Takano
  • Publication number: 20240032437
    Abstract: The present disclosure generally relates to spin-orbit torque (SOT) devices comprising a bismuth antimony (BiSb) layer. The SOT devices further comprises a nonmagnetic buffer layer, a nonmagnetic interlayer, a ferromagnetic layer, and a nonmagnetic barrier layer. One or more of the barrier layer, interlayer, and buffer layer comprise a polycrystalline non-Heusler alloy material, or a Heusler alloy and a material selected from the group consisting of: Cu, Ag, Ge, Mn, Ni, Co, Mo, W, Sn, B, and In. The Heusler alloy is a full Heusler alloy comprising X2YZ or a half Heusler alloy comprising XYZ, where X is one of: Mn, Fe, Co, Ni, Cu, Ru, Rh, Pd, Ag, Ir, Pt, and Au, Y is one of: Ti, V, Cr, Mn, Fe, Co, Ni, Zn, Y, Zr, Nb, Mo, Hf, and W, and Z is one of: B, Al, Si, Ga, Ge, As, In, Sn, Sb, and Bi.
    Type: Application
    Filed: May 15, 2023
    Publication date: January 25, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Quang LE, Brian R. YORK, Cherngye HWANG, Xiaoyong LIU, Susumu OKAMURA, Michael A. GRIBELYUK, Xiaoyu XU, Randy G. SIMMONS, Kuok San HO, Hisashi TAKANO
  • Patent number: 11882361
    Abstract: Aspects of the present disclosure generally relate to optical devices and related methods that facilitate tilt in camera systems, such as tilt of a lens. In one example, an optical device includes a lens, an image sensor disposed below the lens, a plurality of magnets disposed about the lens, and a plurality of: (1) vertical coil structures coiled in one or more vertical planes and (2) horizontal coil structures coiled in one or more horizontal planes. When power is applied, the coil structures can generate magnetic fields that, in the presence of the magnets, cause relative movement of the coil structures and associated structures. The plurality of vertical coil structures are configured to horizontally move the lens. The plurality of horizontal coil structures are configured to tilt the lens when differing electrical power is applied to at least two of the plurality of horizontal coil structures.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: January 23, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Quang Le, Rajeev Nagabhirava, Kuok San Ho, Zhigang Bai, Zhanjie Li, Xiaoyong Liu, Daniele Mauri
  • Patent number: 11875827
    Abstract: The present disclosure generally relate to spin-orbit torque (SOT) devices. The SOT devices each comprise a non-magnetic layer, a free layer disposed in contact with the non-magnetic layer, and a bismuth antimony (BiSb) layer disposed over the free layer. The non-magnetic layer has a thickness of about 0.5 nm to about 2 nm. The BiSb layer has a thickness of about 5 nm to about 10 nm. The BiSb layer and the free layer have collective thickness between about 5 nm to about 20 nm. By reducing the thickness of the non-magnetic layer and BiSb layer, a read gap of each SOT device is reduced while enabling large inverse spin Hall angles and high signal-to-noise ratios.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: January 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Quang Le, Brian R. York, Xiaoyong Liu, Son T. Le, Cherngye Hwang, Michael A. Gribelyuk, Xiaoyu Xu, Kuok San Ho, Hisashi Takano, Julian Sasaki, Huy H. Ho, Khang H. D. Nguyen, Nam Hai Pham
  • Publication number: 20240006109
    Abstract: The present disclosure generally relates to spin-orbit torque (SOT) device comprising a first bismuth antimony (BiSb) layer having a (001) orientation. The SOT device comprises a first BiSb layer having a (001) orientation and a second BiSb layer having a (012) orientation. The first BiSb layer having a (001) orientation is formed by depositing an amorphous material selected from the group consisting of: B, Al, Si, SiN, Mg, Ti, Sc, V, Cr, Mn, Y, Zr, Nb, AlN, C, Ge, and combinations thereof, on a substrate, exposing the amorphous material to form an amorphous oxide surface on the amorphous material, and depositing the first BiSb layer on the amorphous oxide surface. By utilizing a first BiSb layer having a (001) orientation and a second BiSb having a (012) orientation, the signal through the SOT device is balanced and optimized to match through both the first and second BiSb layers.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Quang LE, Brian R. YORK, Cherngye HWANG, Xiaoyong LIU, Michael A. GRIBELYUK, Xiaoyu XU, Randy G. SIMMONS, Kuok San HO, Hisashi TAKANO
  • Publication number: 20240005973
    Abstract: The present disclosure generally relates to spin-orbit torque (SOT) devices comprising a bismuth antimony (BiSb) layer. The SOT devices further comprise one or more GexNiFe layers, where at least one GexNiFe layer is disposed in contact with the BiSb layer. The GexNiFe layer has a thickness less than or equal to about 15 ? when used as an interlayer on top of the BiSb layer or less than or equal to 40 ? when used as a buffer layer underneath the BiSb. When the BiSb layer is doped with a dopant comprising a gas, a metal, a non-metal, or a ceramic material, the GexNiFe layer promotes the BiSb layer to have a (012) orientation. When the BiSb layer is undoped, the GexNiFe layer promotes the BiSb layer to have a (001) orientation. Utilizing the GexNiFe layer allows the crystal orientation of the BiSb layer to be selected.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Quang LE, Brian R. YORK, Cherngye HWANG, Xiaoyong LIU, Michael A. GRIBELYUK, Xiaoyu XU, Susumu OKAMURA, Kuok San HO, Hisashi TAKANO, Randy G. SIMMONS
  • Publication number: 20230420258
    Abstract: A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer.
    Type: Application
    Filed: July 5, 2023
    Publication date: December 28, 2023
    Inventors: Damien Thomas Gilmore, Jonathan P. Davis, Azghar H Khazi-Syed, Shariq Arshad, Khanh Quang Le, Kaneez Eshaher Banu, Jonathan Roy Garrett, Sarah Elizabeth Bradshaw, Eugene Clayton Davis
  • Publication number: 20230419990
    Abstract: The present disclosure generally relates to a bismuth antimony (BiSb) based STO (spin torque oscillator) sensor. The STO sensor comprises a SOT device and a magnetic tunnel junction (MTJ) structure. By utilizing a BiSb layer within the SOT device, a larger spin Hall angle (SHA) can be achieved, thereby improving the efficiency and reliability of the STO sensor.
    Type: Application
    Filed: September 11, 2023
    Publication date: December 28, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Xiaoyong LIU, Zhanjie LI, Quang LE, Brian R. YORK, Cherngye HWANG, Kuok San HO, Hisashi TAKANO
  • Publication number: 20230386721
    Abstract: The present disclosure generally relate to spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices comprising a buffer layer, a bismuth antimony (BiSb) layer having a (012) orientation disposed on the buffer layer, and an interlayer disposed on the BiSb layer. The buffer layer and the interlayer may each independently be a single layer of material or a multilayer of material. The buffer layer and the interlayer each comprise at least one of a covalently bonded amorphous material, a tetragonal (001) material, a tetragonal (110) material, a body-centered cubic (bcc) (100) material, a face-centered cubic (fcc) (100) material, a textured bcc (100) material, a textured fcc (100) material, a textured (100) material, or an amorphous metallic material. The buffer layer and the interlayer inhibit antimony (Sb) migration within the BiSb layer and enhance uniformity of the BiSb layer while further promoting the (012) orientation of the BiSb layer.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Quang LE, Brian R. YORK, Cherngye HWANG, Susumu OKAMURA, Michael A. GRIBELYUK, Xiaoyong LIU, Kuok San HO, Hisashi TAKANO
  • Patent number: 11783853
    Abstract: The present disclosure generally relates to a bismuth antimony (BiSb) based STO (spin torque oscillator) sensor. The STO sensor comprises a SOT device and a magnetic tunnel junction (MTJ) structure. By utilizing a BiSb layer within the SOT device, a larger spin Hall angle (SHA) can be achieved, thereby improving the efficiency and reliability of the STO sensor.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: October 10, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Xiaoyong Liu, Zhanjie Li, Quang Le, Brian R. York, Cherngye Hwang, Kuok San Ho, Hisashi Takano
  • Patent number: 11784791
    Abstract: An online identity can be verified based on data from multiple identity sources stored in a blockchain. For example, a request for a token is received from an entity for authenticating an online identity of the entity to an online service. The request can be stored in a blockchain that represents the online identity of the entity by adding a new block to the blockchain. The new block can include data indicating the request for the token. The token can be generated based on the one or more ordered blocks in the blockchain. The token can be transmitted to the entity. The token can be received from the online service. Confirmation of the online identity of the entity can be transmitted to the online service based on receiving the token from the online service.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: October 10, 2023
    Assignee: Equifax Inc.
    Inventors: Sri Krishnamacharya, Quang Le, Stan Tigrett, Russ Ayres
  • Publication number: 20230317163
    Abstract: An apparatus and system are described to provide an in-memory computing non-volatile flash memory cell array used in a neural network. Each cell includes a Resistive RAM memory (RRAM) and a physical resistor formed from a high resistive material. The RRAM is programmed to either an on or off state in which the resistance is respectively significantly less or more than the resistor to permit the RRAM to act as a switch and allow for in-situ training. Multi-bit RRAM cells contain multiple RRAMs, each of which is connected to a resistor having a different resistance and read using the same input line. The resistors are formed from the same material as the resistor in the analog-to-digital converter used to read the array.
    Type: Application
    Filed: March 23, 2023
    Publication date: October 5, 2023
    Inventor: Binh Quang Le
  • Patent number: 11776565
    Abstract: The present disclosure generally relates to a tape head of a tape drive, and methods of forming thereof. In one embodiment, a tape head for magnetic storage devices comprises a trailing shield, a leading shield, a first write pole coupled to the trailing shield, a second write pole coupled to the leading shield, and side shields spaced from the first write pole and the second write pole by a thin insulation layer. The side shields are further disposed between the trailing shield and the leading shield. In another embodiment, a tape head for magnetic storage devices comprises a main pole disposed between a trailing shield and a leading shield and a side shield disposed adjacent to the main pole. The side shield is further disposed between the trailing shield and the leading shield and spaced from the main pole by a thin insulation layer.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: October 3, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Quang Le, Hongquan Jiang, Cherngye Hwang, David J. Seagle, Xiaoyong Liu
  • Patent number: 11776567
    Abstract: The present disclosure generally relates to spin-orbital torque (SOT) differential reader designs. The SOT differential reader is a multi-terminal device comprising a first seed layer, a first spin hall effect (SHE) layer, a first interlayer, a first free layer, a gap layer, a second seed layer, a second SHE layer, a second free layer, and a second interlayer. The gap layer is disposed between the first SHE layer and the second SHE layer. The materials and dimensions used for the first and second seed layers, the first and second interlayers, and the first and second SHE layers affect the resulting spin hall voltage converted from spin current injected from the first free layer and the second free layer, as well as the ability to tune the first and second SHE layers. Moreover, the SOT differential reader improves reader resolution without decreasing the shield-to-shield spacing (i.e., read-gap).
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: October 3, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Cherngye Hwang, Xiaoyong Liu, Quang Le, Kuok San Ho, Hisashi Takano, Brian R. York
  • Publication number: 20230306993
    Abstract: The present disclosure generally relate to spin-orbit torque (SOT) devices. The SOT devices each comprise a non-magnetic layer, a free layer disposed in contact with the non-magnetic layer, and a bismuth antimony (BiSb) layer disposed over the free layer. The non-magnetic layer has a thickness of about 0.5 nm to about 2 nm. The BiSb layer has a thickness of about 5 nm to about 10 nm. The BiSb layer and the free layer have collective thickness between about 5 nm to about 20 nm. By reducing the thickness of the non-magnetic layer and BiSb layer, a read gap of each SOT device is reduced while enabling large inverse spin Hall angles and high signal-to-noise ratios.
    Type: Application
    Filed: March 25, 2022
    Publication date: September 28, 2023
    Inventors: Quang LE, Brian R. YORK, Xiaoyong LIU, Son T. LE, Cherngye HWANG, Michael A. GRIBELYUK, Xiaoyu XU, Kuok San HO, Hisashi TAKANO, Julian SASAKI, Huy H. HO, Khang H. D. NGUYEN, Nam Hai PHAM
  • Patent number: 11763973
    Abstract: The present disclosure generally relate to spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices comprising a buffer layer, a bismuth antimony (BiSb) layer having a (012) orientation disposed on the buffer layer, and an interlayer disposed on the BiSb layer. The buffer layer and the interlayer may each independently be a single layer of material or a multilayer of material. The buffer layer and the interlayer each comprise at least one of a covalently bonded amorphous material, a tetragonal (001) material, a tetragonal (110) material, a body-centered cubic (bcc) (100) material, a face-centered cubic (fcc) (100) material, a textured bcc (100) material, a textured fcc (100) material, a textured (100) material, or an amorphous metallic material. The buffer layer and the interlayer inhibit antimony (Sb) migration within the BiSb layer and enhance uniformity of the BiSb layer while further promoting the (012) orientation of the BiSb layer.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: September 19, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Quang Le, Brian R. York, Cherngye Hwang, Susumu Okamura, Michael Gribelyuk, Xiaoyong Liu, Kuok San Ho, Hisashi Takano
  • Patent number: 11742208
    Abstract: A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: August 29, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Damien Thomas Gilmore, Jonathan P. Davis, Azghar H Khazi-Syed, Shariq Arshad, Khanh Quang Le, Kaneez Eshaher Banu, Jonathan Roy Garrett, Sarah Elizabeth Bradshaw, Eugene Clayton Davis
  • Patent number: 11735211
    Abstract: The present disclosure relates to read head apparatus, and methods of forming read head apparatus, for magnetic storage devices, such as magnetic tape drives (e.g., tape drives). In one implementation, a read head for magnetic storage devices includes a lower shield, one or more upper shields, one or more lower leads, and a plurality of upper leads. The read head includes a plurality of read sensors, each read sensor of the plurality of read sensors including a first antiferromagnetic (AFM) layer. The read head includes a plurality of soft bias side shields disposed between and outwardly of the plurality of read sensors. The read head includes one or more second AFM layers disposed above the first AFM layer and the plurality of soft bias side shields along a downtrack direction.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: August 22, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Quang Le, Hongquan Jiang, Cherngye Hwang, Hisashi Takano
  • Publication number: 20230223043
    Abstract: The present disclosure generally relates to a tape head of a tape drive, and methods of forming thereof. In one embodiment, a tape head for magnetic storage devices comprises a trailing shield, a leading shield, a first write pole coupled to the trailing shield, a second write pole coupled to the leading shield, and side shields spaced from the first write pole and the second write pole by a thin insulation layer. The side shields are further disposed between the trailing shield and the leading shield. In another embodiment, a tape head for magnetic storage devices comprises a main pole disposed between a trailing shield and a leading shield and a side shield disposed adjacent to the main pole. The side shield is further disposed between the trailing shield and the leading shield and spaced from the main pole by a thin insulation layer.
    Type: Application
    Filed: January 12, 2022
    Publication date: July 13, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Quang LE, Hongquan JIANG, Cherngye HWANG, David J. SEAGLE, Xiaoyong LIU
  • Patent number: 11694713
    Abstract: A spin-orbit torque (SOT) magnetic tunnel junction (MTJ) device includes a substrate, a buffer layer formed over the substrate, and a bismuth antimony (BiSb) layer formed over the buffer layer, the BiSb layer having a (012) orientation. In certain embodiments, the SOT MTJ device is part of a microwave assisted magnetic recording (MAMR) write head. In certain embodiments, the SOT MTJ device is part of a magnetoresistive random access memory (MRAM) device.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: July 4, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Quang Le, Cherngye Hwang, Brian R. York, Thao A. Nguyen, Zheng Gao, Kuok San Ho, Pham Nam Hai